• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.32-41
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• 1996

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.1
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• pp.54-61
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• 2000

Conventionally, ZVS FB DC/DC converter was controlled by monolithic IC UC3879, which includes the functions of oscillator, error amplifier and phase-shift circuit. Also, microprocessor and DSP have been widely used for the remote control and for the immediate waveform control in ZVS FB DC/DC converter. However the conventional microprocessor controller is complex and difficult to control because the controller consists of analog and digital parts. In the case of the control of FB DC/DC converter, the output is required of driving a direct signal to the switch drive circuits by the digital controller. So, this paper presents the method and realization of designing the digital-to-phase shift PWM circuit controlled by DSP (TMX320C32) in a 2,500A, 40㎾ ZVS FB DC/DC converter.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.1-6
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• 2012

Using a current-mode multiple reset, a current-to-voltage(I-V) converter with a wide dynamic range was produced. The converter consists of a trans-impedance amplifier(TIA), an analog-to-digital converter(ADC), and an N-bit counter. The digital output of the I-V converter is composed of higher N bits and lower bits, obtained from the N-bit counter and the ADC, respectively. For an input current that has departed from the linear region of the TIA, the counter increases its digital output, this determines a reset current which is subtracted from the input current of the I-V converter. This current-mode reset is repeated until the input current of the TIA lies in the linear region. This I-V converter is realized using 0.35 ${\mu}m$ LSI technology. It is shown that the proposed I-V converter can increase the maximum input current by a factor of $2^N$ and widen the dynamic range by $6^N$. Additionally, the I-V converter is successfully applied to a photometric sensor.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.6
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• pp.87-93
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• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.160-164
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• 2000

Digital to analog converters based on the Josephson effect are promising for voltage standard, because they produce voltage steps with high precision and good stability. In this paper, we made a simulation study on RSFQ D/A converter. RSFQ D/A converter was composed of NDRO cells, T(toggle) flip-flops, D flip-flops, Splitters and Confluence Buffers. Confluence Buffer was used to reset the D/A converter. We also obtained operating margins of the important circuit values by simulational experiments.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.5
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• pp.1-9
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• 1971

An analog to digital converter Ivhich is applicable to mass production of digital multimeter is developed. The solid state digital instrument has accuracy $\pm$0.1% of feading $\pm$1 digit over 1 mV to 1000 volts with high input impedance and automatic function. All possibility to affect the distortion of A/D converter is tudied. As a result, useful linearity with high temperature stability of integrating waveforms is achieved by the very simplified circuit configuration to assure the proposed accuracy under various ambient condition.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.