• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1254-1259
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• 2008

A new CMOS current-mode integrator for low-voltage analog integrated circuit design is presented. The proposed current-mode integrator is based on cross-coupled gain-boosting topology. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed current-mode integrator achieves high current gain and unity gain frequency with the same transistor size. As a application circuit of the proposed integrator, we designed the 1.8V 200MHz band current-mode lowpass filter. These are verified by Hspice simulation using $0.18{\mu}m$ CMOS technology.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.571-573
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• 1988

A new ripple analog-to-digital converter(ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the input signal in two serial steps. First a coarse conversion is made to determine the most significant bits by the first parallel ADC. The results control a switching network to connect the series resistor segment, the analog signal is contained within, to the second parallel ADC. At second step, a fine conversion is made to determine the least signification bits by the second parallel ADC. The circuit requires 2(2$\frac{N}{2}$) comparators, 2(2$\frac{N}{2}$) resistors, and 2(2$\frac{N}{2}$) switches for N-bit resolution.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.2
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• pp.87-92
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• 2001

This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is $2{\times}2$, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2${\mu}m$ double poly CMOS parameters of MOSIS fabrication process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.522-523
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• 2017

Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.127-130
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• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.299-302
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• 1999

An analog implementation of space vector PWM is proposed in this paper. It is shown that a space vector PWM can be implemented by adding a zero sequency voltage to reference voltage of triangle comparison PWM. The proposed scheme is implemented by six diodes and, an operational amplifier circuit and, a few resistors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.3-3
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• 2010

The Characteristics of Digital Vterbi Decoder utilizing the analog parallel processing circuit technology is proposed. The Analog parallel structure of the viterbi decoder acted by a replacement of the conventional digital viterbi Decoder is progressing fastly. The proposed circuits design han, low distortion, high accuracy over the previous implementation and dynamic programming.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.229-232
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• 2005

This paper presents the OTA-based current differencing buffered amplifier (CDBA), which has a simple configuration comprised four OTAs. The proposed circuit is ease of design and suitable for analog signal processing applications in both voltage and current modes. The first order allpass filters were implemented as the application examples in order to demonstrate the performances of the proposed CDBA. PSPICE analog simulation and the commercially available OTAs-based experimental results verifying the circuit performances are also included.

• Proceedings of the IEEK Conference
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• 2000.11c
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• pp.149-152
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• 2000

We propose simple analog MOS circuits producing the one-dimensional compact motion-sensing circuits. In the proposed circuit, the optical flow is computed by a number of local motion sensors which are based on biological motion detectors. Mimicking the structure of biological motion detectors made the circuit structure quite simple, compared with conventional velocity sensing circuits. Extensive simulation results by a simulation program of integrated circuit emphasis (SPICE) indicated that the proposed circuits could compute local velocities of a moving light spot and showed direction selectivity for the moving spot