• International Journal of Internet, Broadcasting and Communication
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• v.12 no.2
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• pp.77-82
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• 2020

IoT devices frequently require input resources to communicate with various sensors or IoT platforms. IoT device wastes a lot of time as idle time or waiting time to check the data of the input resource and use the input resource. In addition, IoT devices use various input resources. We compares and analyzes input idle time and input waiting time generated from hardware serial input resource, software serial input resource, digital port input resource, and analog port input resource using Arduino widely used as IoT device. In order to design the IoT device framework, it is necessary to understand the characteristics of input resources and to design them to minimize unnecessary input idle time and input waiting time. The analog input wait time has a much larger input wait time than the digital input wait time, so it must be designed to receive analog information periodically at the appropriate timing. The characteristics of the input resources analyzed in this way help to design an efficient IoT device.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.33-41
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• 2019

We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

• Smart Structures and Systems
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• v.19 no.5
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• pp.487-497
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• 2017

Semi-active devices use the building's own motion to produce resistive forces and are thus strictly dissipative and require little power. Devices that independently control the binary open/closed valve state can enable novel device hysteresis loops that were not previously possible. However, some device hysteresis loops cannot be obtained without active analog valve control allowing slower, controlled release of stored energy, and is presents an ongoing limitation in obtaining the full range of possibilities offered by these devices. This in silico study develops a proportional-derivative feedback control law using a validated nonlinear device model to track an ideal diamond-shaped force-displacement response profile using active analog valve control. It is validated by comparison to the ideal shape for both sinusoidal and random seismic input motions. Structural application specific spectral analysis compares the performance for the non-linear, actively controlled case to those obtained with an ideal, linear model to validate that the potential performance will be retained when considering realistic nonlinear behaviour and the designed valve control approach. Results show tracking of the device force-displacement loop to within 3-5% of the desired ideal curve. Valve delay, rather than control law design, is the primary limiting factor, and analysis indicates a ratio of valve delay to structural period must be 1/10 or smaller to ensure adequate tracking, relating valve performance to structural period and overall device performance under control. Overall, the results show that active analog feedback control of energy release in these devices can significantly increase the range of resetable, valve-controlled semi-active device performance and hysteresis loops, in turn increasing their performance envelop and application space.

• Journal of the Korean Chemical Society
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• v.25 no.2
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• pp.103-109
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• 1981

An inexpensive, yet convenient analog storage device was constructed. Sequentially MOSFET-switched 20 sample and holds equipped with a high input impedance preamplifier were parallelly matched to the digitally controlled shift register system in variable speeds up to 3 kHz. To verify its usefulness, square wave train, sinusiodal wave and some electrochemical data, such as fast-scan voltammogram and transient current-time curves of differential pulse polarography were tested.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.431-434
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• 2008

The physical OLED analog behavioral model for SPICE simulation has been described using Verilog-A language. The model is based on the carrier-balance between the hole and electron injected through Schottky barrier at anode and cathode. The accuracy of this model was examined by comparing with the results from device simulation.

• Journal of Information Display
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• v.10 no.3
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• pp.101-106
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• 2009

In this study, a physical OLED analog behavior model for SPICE simulation was described using the Verilog-A language. The model was presented through theoretical equations for the J-V characteristics of OLED derived according to the internalcarrier emission equation based on a diffusion model at the Schottky barrier contact, and the mobility equation based on the Pool-Frenkel model. The accuracy of this model was examined by comparing it with the results of the device simulation that was conducted.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.35-42
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• 2013

In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.

• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.