• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.575-578
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• 1998

In this paper, we propose a VLSI architecture of Reed-Solomon decoder. Our goal is the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. To achieve the this goal, we analyze the RS decoding algorithm to be used parallel and pipelined processing efficiently, and modified the Euclid's algorithm arithmetic part to apply the parallel structure in RS decoder. The overall RS decoder are compared to Shao's, and we show the 10% area efficiency than Shao's time domain decoder and three times faster, in addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemeted with LG 0.6{\mu}$ processing.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.730-732
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• 2005

최근 이미지 압축, 워터마킹 또는 스케일러블 비디오 코딩 분야에서 DCT와 DWT 연산을 선택적으로 사용하거나, 혼합하여 사용하는 경우가 늘어나고 있다. 이러한 두개의 연산을 사용하는 방법은 소프트웨어적인 프로그램을 사용하거나 하드웨어를 따로 구현하여 사용하였다. 본 연구에서는 하나의 모듈로 두개의 연산을 수행할 수 있는 재구성 하드웨어를 제안한다. 또한 DCT와 DWT연산에 있어서, 가장 많은 연산을 수행하는 부분은 계수(Coefficient)값과 입력 값의 내적 연산(Inner Product)을 수행하는 것인데, 이 내적연산을 하는데 있어서 곱셈기를 사용하지 않는 분산연산을 사용함으로써 연산의 복잡도를 줄이고, 하드웨어의 속도를 빠르게 하였다. 실험 환경은 Altera FPGA를 사용한 Excalibur_ARM (EPXA10F1020Cl) 보드를 이용하여 구현하였으며, 동작속도는 47.85MHz이다.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.327-330
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• 2008

This paper shows an implementation of WLAN-based Audio/Video(A/V) system for multimedia home networks. Proposed WLAN-based A/V system can transmit multimedia data of high quality. The entire system consists of a 16-bit RISC controller, a program ROM, a SRAM, timers, an interrupt controller, a DART, GPIOs, an I2C and the OFDM modem supporting for the IEEE 802.11g standard. The simple MAC functions are implemented by firmware on an embedded 16-bit RISC controller. The OFDM modem supports a complete set of data rates up to 54Mbps. Proposed the system is implemented by an Altera FPGA EP1S60F1020C6 device, a 10-bit 2-ch DAC, a 10-bit 2-ch ADC and RF/IF chips.

• Journal of Power Electronics
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• v.15 no.4
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• pp.964-973
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• 2015

This paper presents a simple approach for the selective harmonic elimination (SHE) of multilevel inverter based on the transistor-clamped H-bridge (TCHB) family. The SHE modulation is derived from the sinusoidal voltage-angle equal criteria corresponding to the optimized switching angles. The switching angles are computed offline by solving transcendental non-linear equations characterizing the harmonic contents using the Newton-Raphson method to produce an optimum stepped output. Simulation and experimental tests are conducted for verification of the analytical solutions. An Altera DE2 field-programmable gate array (FPGA) board is used as the digital controller device in order to verify the proposed SHE modulation in real-time applications. An analysis of the voltage total harmonic distortion (THD) has been obtained for multiple output voltage cases. In terms of the THD, the results showed that the higher the number of output levels, the lower the THD due to an increase number of harmonic orders being eliminated.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.809-812
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• 2002

본 논문은 RSA 암호시스템에서 고속 모듈러 곱셈을 위한 최적화된 시스톨릭 어레이의 설계를 제안한다. 제안된 방법에서는 미리 계산된 가산결과를 사용하여 개선된 몽고메리 모듈러 곱셈 알고리듬을 제안하고, 고속 모듈러 곱셈을 위한 새로운 구조의 시스톨릭 어레이를 설계한다. 미리 계산된 가산결과를 얻기 위해 CLA(Carry Look-ahead Adder)를 사용하였으며, 이 가산기는 덧셈연산에 있어서 캐리전달 지연이 제거되므로 연산 속도를 향상 시킬 수 있다. 제안된 시스톨릭 구조는VHDL(VHSlC Hardware Description Language)을 사용하여 동작적 수준을 기술하였고, Ultra 10 Workstation 상에서 $Synopsys^{TM}$ 툴을 사용하여 합성 및 시뮬레이션을 수행하였다. 또한, FPGA 구현을 위하여 Altera MaxplusII를 사용하여 타이밍 시뮬레이션을 수행하였고, 실험을 통하여 제안한 방법을 효율성을 확인하였다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.411-413
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• 2003

본 논문에서는 ARM922T Core와 주변장치를 설계할 수 있는 100만 게이트의 FPGA를 내장한 알데라(Altera)사의 엑스칼리버(Excalibur)를 이용하여 DC모터 제어용 SoC를 설계하였다. SoC란 System on Chip의 약자로 하나의 칩 안에 프로세서와 다양한 목적의 주변장치들을 집적하는 것을 말한다. 모터를 구동하기 위한 PWM신호 생성기를 하드웨어 설계언어(Hardware Description Language)로 구현하고 시뮬레이션을 통해 설계모듈을 검증하였다. 이렇게 검증한 PWM 생성기 모듈과 ARM922T Core를 합성하여 SoC를 설계하였다. PWM 생성기 모들을 구성하는 내부의 각 분분을 VerilogHDL로 코딩하여 심볼로 만들어 통합하는 방식으로 설계를 하였으며 실제 모터를 구동하기 위해서 프로세서가 동작할 수 있도록 C언어로 프로그램하여 함께 칩에 다운로드하여 테스트를 하였다. SoC를 기반으로한 시스템 설계의 장점은 시스템이 간단해지고 고속의 동작이 가능하며 회로의 검증 및 다양한 시뮬레이션이 용이하다는데 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.62-71
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• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.

• Journal of Advanced Navigation Technology
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• v.21 no.6
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• pp.554-560
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• 2017

Accurate altimetry is required for the reliable flight control of drones or unmanned air vehicles (UAVs), and the radar altimeter is commonly used owing to its accuracy for the ground level. Due to the limitation for size, weight and power consumption, the frequency modulated continuous wave (FMCW) radar is appropriate for drone because it has lower complexity than that of pulse Doppler (PD) radar. Especially, fast-ramp FMCW radar, which transmits linear FM signal during very short period, is generally utilized, because it is robust for the ego-motion of drone. Therefore, we present the design and implementation results of the radar signal processor (RSP) for fast-ramp FMCW radar system. The proposed RSP was designed with Verilog-HDL and implemented with Altera Cyclone-IV FPGA device. Implementation results show that the proposed RSP includes 27,523 logic elements, 15,798 registers and memory of 138Kbits and can measure the altimeter at the rate of 100Hz with the operating frequency of 50MHz.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.511-516
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• 2006

In this raper, we propose the Sequentiel Couleur Avec Memoire or Sequential Color with Memory (SECAM) video encoder system using modified anti-cloche filters and the SECAM video decoder system using a band pass filter (BPF) and an error-free square root. The SECAM encoder requires an anti-cloche filter recommended by International Telecommunication Union-Recommendation (ITU-R) Broadcasting service Television (BT) 470. However, the design of the anti-cloche filter is difficult because the frequency response of the anti-cloche filter is very sharp around rejection-frequency area. So, we convert the filter into a hish pass filter (HPF) by shifting the rejection frequency of 4.286MHz to 0Hz frequency. The design of HPF becomes very easy, compared to that of the anti-cloche filter. The proposed decoder also uses an error-free square root, two differentiators and trigonometric functions to extract color-component information of Db and Dr accurately from frequency modulation (FM) signals in SECAM systems. Also, the BPF in decoder it used for removing color noise in chrominance and dividing CVBS into chrominance and luminance. The proposed systems are experimentally demonstrated with Altera FPGA APEX20KE EP20K1000EBC652-3 device and TV sets.