• Journal of the Korean Ceramic Society
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• v.22 no.6
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• pp.37-41
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• 1985

Several $Al_2O_3$-based polycrystalline which had different dopant ratio in the range of 0.5mol% were prepared by doping pure $Cr_2O_3$, $ZrO_2$, $HfO_3$ Single crystalline which had same composition with above polycrystalline were made by means of floating zone method. This study examined the role of each dopant for enhancing the mefchanical properties of $Al_2O_3$-based Ceramics. Optical micrographs $({\times}200)$ of $Al_2O_3-Cr_2O_3$ single crystal showing not only radial crack (rc) on the specimen surface but median crack (mc) and lateral crack (lc) under surface at the edge of indentation mark. Fracture toughness of $Al_2O_3$-based Ceramics was increased with $ZrO_2$ content. Alloying effect of $Cr_2O_3$ contributed to the hardness of $Al_2O_3$ based ceramics.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.373-373
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• 2014

Resistive-change random access memory (ReRAM) device is one of the promising candidates owing to its simple structure, high scalability potential and low power operation. Many resistive switching devices using transition metal oxides materials such as NiO, Al2O3, ZnO, HfO2, $TiO_2$, have attracting increased attention in recent years as the next-generation nonvolatile memory. Among various transition metal oxides materials, HfO2 has been adopted as the gate dielectric in advanced Si devices. For this reason, it is advantageous to develop an HfO2-based ReRAM devices to leverage its compatibility with Si. However, the annealing temperature of these high-k thin films for a suitable resistive memory switching is high, so there are several reports for low temperature process including microwave irradiation. In this paper, we demonstrate the bipolar resistive switching characteristics in the microwave irradiation annealing processed Ag/HfO2/Pt ReRAM device. Compared to the as-deposited Ag/HfO2/Pt device, highly improved uniformity of resistance values and operating voltage were obtained from the micro wave annealing processed HfO2 ReRAM device. In addition, a stable DC endurance (>100 cycles) and a high data retention (>104 sec) were achieved.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.211-211
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• 2009

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.158-158
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• 2009

This paper focuses on improving organic thin film transistor (OTFT) characteristics by controlling the self-organization of pentacene molecules with an alignable high-dielectric-constant film. The process, based on the growth of pentacene film through high-vacuum sublimation, is a method of self-organization using ion-beam (IB) bombardment of the $HfO_2/Al_2O_3$ surface used as the gate dielectric layer. X-ray photoelectron spectroscopy indicates that the IB raises the rate of the structural anisotropy of the $HfO_2/Al_2O_3$film, and X-ray diffraction patterns show the possibility of increasing the anisotropy to create the self-organization of pentacene molecules in the first polarized monolayer. An effective mobility of $2.3{\times}10^{-3}cm^2V^{-1}s^{-1}$ was achieved, which is significantly different from that of pentacene films that are not aligned. The proposed OTFT devices with an ultrathin $HfO_2$ structure as the gate dielectric layer were operated at a gate voltage lower than 5 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.710-712
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• 2011

In this study, we fabricate resistive switching random access memory (ReRAM) devices constructed with a Al/$HfO_2$/ITO structure on glass substrates and investigate their memory characteristics. The hafnium oxide thin film used as a resistive switching layer is sputtered at room temperature in a sputtering system with a cooling unit. The Al/$HfO_2$/ITO device exhibits bipolar resistive switching characteristics, and the ratio of the high resistance (HRS) to low resistance states (LRS) is more than 60. In addition, the resistance ratio maintains even after $10^4$ seconds.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.288-288
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• 2011

최근 Charge Trap Flash (CTF) Non-Volatile Memory (NVM) 소자가 30 nm node 이하로 보고 되면서, 고집적화 플래시 메모리 소자로 각광 받고 있다. 기존의 CTF NVM 소자의 tunnel layer로 쓰이는 SiO2는 성장의 용이성과 Si 기판과의 계면특성, 낮은 누설전류와 같은 장점을 지니고 있다. 하지만 단일층의 SiO2를 tunnel layer로 사용하는 기존의 Non-Valatile Memory (NVM)는 두께가 5 nm 이하에서 direct tunneling과 Stress Induced Leakage Current (SILC) 등의 효과로 인해 게이트 누설 전류가 증가하여 메모리 보존특성의 감소와 같은 신뢰성 저하에 문제점을 지니고 있다. 이를 극복하기 위한 방안으로, 최근 CTF NVM 소자의 Tunnel Barrier Engineered (TBE) 기술이 많이 접목되고 있는 상황이다. TBE 기술은 SiO2 단일층 대신에 서로 다른 유전율을 가지는 절연막을 적층시킴으로서 전계에 대한 민감도를 높여 메모리 소자의 쓰기/지우기 동작 특성과 보존특성을 동시에 개선하는 방법이다. 또한 터널링 절연막으로 유전률이 큰 High-K 물질을 이용하면 물리적인 두께를 증가시킴으로서 누설 전류를 줄이고, 단위 면적당 gate capacitance값을 늘릴 수 있어 메모리 소자의 동작 특성을 개선할 수 있다. 본 연구에서는 CTF NVM 소자의 trap layer로 쓰이는 HfO2의 두께를 5 nm, blocking layer의 역할을 하는 Al2O3의 두께를 12 nm로 하고, tunnel layer로 Si3N4막 위에 유전율과 Energy BandGap이 유사한 HfAlO와 ZrO2를 적층하여 Program/Erase Speed, Retention, Endurance를 측정을 통해 메모리 소자로서의 특성을 비교 분석하였다.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.66-67
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• 2002

Magnetic tunnel junction에서는 spin의 tunneling이 가장 기본적인 현상이기 때문에 tunnel junction의 특성은 tunnel barrier의 성질에 크게 의존한다. Tunnel barrier로는 지금까지 $Al_2$O$_3$가 주로 사용되고 있다. 하지만 $Al_2$O$_3$의 경우는 barrier height가 2-3 eV로 높기 때문에 저 저항의 tunnel junction을 형성하기 위해서는 Al의 두께가 1nm 이하로 낮아져야 한다. 따라서 이를 극복하기 위해서 $Al_2$O$_3$ 보다 낮은 barrier height를 갖는 절연막을 tunnel barrier로 사용하고자 하는 연구가 많이 진행되고 있다 (예를 들면 TaOx [1], ZrOx [2], GaOx [3], and HfOx [4]). (중략)

• Applied Chemistry for Engineering
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• v.9 no.5
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• pp.629-633
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• 1998

The synthesis of 1,1-difluoroethane from acetylene as a function of HF/acetylene ratio, contact time and reaction temperature was studied on a fluorinated ${\gamma}-Al_2O_3$. The fluorination of ${\gamma}-Al_2O_3$ was treated with pure HF gas at high temperature. The crystallinity, the porosity, and the acid properties of the prepared samples were examined using XRD, the nitrogen adsorption, pyridine-IR and ammonia-TPD respectively. The activity was enhanced by further fluorination of alumina. The fraction of 1,1-difluoroethane was obtained above 90% at reaction temperature of about $200^{\circ}C$. The ratio of 1,1-difluoroethane to vinylfluoride over fluorinated ${\gamma}-Al_2O_3$ catalyst was increased with the mole ratio of HF/acetylene and contact time, and was found to be the highest ratio at reaction temperature of $200^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.358-358
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• 2010

To improve the programming/erasing speed and leakage current of multiple dielectric stack tunnel barrier engineering (TBE) Non-volatile memory, We propose a new concept called staggered structure of TBE memory. In this study, We fabricated staggered structure capacitor on $Si_3N_4$ stacked HfAlO and measured C-V curve that can observe tunneling characteristic of this device as various annealing temperature compared with that of single layer $SiO_2$ capacitor.