• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• Journal of Korea Multimedia Society
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• v.16 no.10
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• pp.1156-1162
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• 2013

Face verification has been widely studied during the past two decades. One of the challenges is the rising concern about the security and privacy of the template database. In this paper, we propose a secure face verification system which generates a unique secure cryptographic key from a face template. The face images are processed to produce face templates or codes to be utilized for the encryption and decryption tasks. The result identity data is encrypted using Advanced Encryption Standard (AES). Distance metric naming hamming distance and Euclidean distance are used for template matching identification process, where template matching is a process used in pattern recognition. The proposed system is tested on the ORL, YALEs, and PKNU face databases, which contain 360, 135, and 54 training images respectively. We employ Principle Component Analysis (PCA) to determine the most discriminating features among face images. The experimental results showed that the proposed distance measure was one the promising best measures with respect to different characteristics of the biometric systems. Using the proposed method we needed to extract fewer images in order to achieve 100% cumulative recognition than using any other tested distance measure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.359-362
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• 2014

With recent growing of application service, servers are required to sustain great amount of data and to handle them quickly: besides, data must be processed securely. The main security algorithm used in security services of server is AES(Advanced Encryption Standard - 2001 published by NIST), which is widely accepted in the world market for superiority of performance. In Korea, NSRI(National Security Research Institute) has developed ARIA(Academy, Research Institute, Agency) algorithm in 2004 and LEA(Lightweight Encryption Algorithm) algorithm in 2012. In this paper, we show advantage of LEA by comparing performance with AES and ARIA in various servers.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.494-503
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• 2003

In this paper, we propose the implementation techniques of IC card chipset that is compatible with international standard ISO-7816 and supports WindowsCE operating system to expropriate various electronic cash and credit card. This IC card interface chip set is composed with 32 bit ARM720T Core and AES(Advanced Encryption System) cryptography module for electronic commerce. Six IC card interfaces support T=0, T=1 protocol and two of them are used to interface with user card directly, the others are used for interface with SAM card. In addition, It supports a LCD controller and USB interface for host. We improved the performance about 70% than software based It card chip set and verified using Hynix 0.35um process.

• Journal of information and communication convergence engineering
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• v.10 no.3
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• pp.248-252
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• 2012

The sensor network standard DASH7 was proposed to improve transmission quality and low power communication. Specifications for the standard are currently being developed, so the security specification has not been firmly implemented. However, without a security specification, a network cannot work due to threats from malicious users. Thus we must ensure confidentiality and authentication of data packets by using a cryptography method. To contribute to the DASH7 security specification, this paper shows the implementation results of network and data link layer security by using advanced encryption standard (AES) counter with CBC-MAC (CCM) over CC430 sensor nodes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.

• ETRI Journal
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• v.39 no.1
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• pp.108-115
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• 2017

ARIA is a 128-bit block cipher that has been selected as a Korean encryption standard. Similar to AES, it is robust against differential cryptanalysis and linear cryptanalysis. In this study, we analyze the security of ARIA against differential-linear cryptanalysis. We present five rounds of differential-linear distinguishers for ARIA, which can distinguish five rounds of ARIA from random permutations using only 284.8 chosen plaintexts. Moreover, we develop differential-linear attacks based on six rounds of ARIA-128 and seven rounds of ARIA-256. This is the first multidimensional differential-linear cryptanalysis of ARIA and it has lower data complexity than all previous results. This is a preliminary study and further research may obtain better results in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Journal of IKEEE
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• v.24 no.3
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• pp.791-796
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• 2020

In this paper, "Q-Bone", a 3^rd generation blockchain platform with enhanced security and flexibility, was developed. As a 3^rd generation blockchain platform, it exploits BP (block producer) to increase processing speed. It has many advantages as follows. It improves both security and speed by mixing RSA (Rivest-Shamir-Adleman) and AES (advanced encryption standard). It improves flexibility by exploiting gateway to convert between apps and blockchain with different programming language. It increases processing speed by combining whole transactions into one block and distribute it when too many transactions occur. It improves search speed by inserting sequence hash into transaction data. It was implemented and applied to pet communication service and academy-instructor-student matching service, and it was verified to work correctly and effectively. Its processing speed is 3,357 transactions/second, which shows excellent performance.

• Journal of the Korea Society of Computer and Information
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• v.16 no.11
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• pp.163-171
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• 2011

Because RFID systems use radio frequency, they have many security problems such as eavesdropping, location tracking, spoofing attack and replay attack. So, many mutual authentication protocols and cryptography methods for RFID systems have been proposed in order to solve security problems, but previous proposed protocols using AES(Advanced Encryption Standard) have fixed key problem and security problems. In this paper, we analyze security of proposed protocols and propose our protocol using OTP(One-Time Pad) and AES to solve security problems and to reduce hardware overhead and operation. Our protocol encrypts data transferred between RFID reader and tag, and accomplishes mutual authentication by one time random number to generate in RFID reader. In addition, this paper presents that our protocol has higher security and efficiency in computation volume and process than researched protocols and S.Oh's Protocol. Therefore, our protocol is secure against various attacks and suitable for lightweight RFID tag system.