• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• ETRI Journal
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• v.30 no.6
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• pp.850-852
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• 2008

This letter presents a power efficient 64-state Viterbi decoder (VD) employing a two-stage radix-4 add-compare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency-division multiplexing (MB-OFDM) ultra-wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-${\mu}m$ CMOS technology.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.863-866
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• 1999

In this paper, we designed a Viterbi decoder with constraint length K=7, code rate R=1/2, encoder generator polynomial (171, 133)$_{8}$. This decoder makes use of 3-bit soft decision. We designed the Viterbi decoder using VHDL. We employed conventional logic circuit instead of ROM for branch metric units(BMUs) to reduce the number of gates. We adopted fully parallel structures for add-compare-select units(ACSUs). The size of the designed decoder is about 200, 000 gates.s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.1-8
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• 2004

Viterbi decoders are widely used for communication and high-density storage devices. An add-compare-select(ACS) unit has been an active research area for a long time because it is the most critical component in determining the operation speed and power-consumption of the Viterbi decoder. We propose a new comparator which is faster and consumes less power than existing ones. We also used the new comparator for a Viterbi decoder and our simulations results show the Viterbi decoder outperforms existing ones at least $20\%$ in its operating speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3A
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• pp.217-225
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• 2005

This paper presents specialized DSP instructions and their architecture for the Viterbi algorithm used in various wireless communication standards. The proposed architecture can significantly reduce the Trace Back (TB) latency. The proposed instructions perform the Add Compare Select (ACS) and TB operations in parallel and the architecture has special hardware, called the Offset Calculation Unit (OCU), which automatically calculates data addresses for the trellis butterfly computations. Logic synthesis has been Performed using the Samsung SEC 0.18 μm standard cell library. OCU consists of 1,460 gates and the maximum delay of OCU is about 5.75 ns. The BER performance of the ACS-TB parallel method increases about 0.00022dB at 6dB Eb/No compared with the typical TB method, which is negligible. When the constraint length K is 5, the proposed DSP architecture can reduce the decoding cycles about 17% compared with the Carmel DSP and about 45% compared with 7MS320c15x.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.81-89
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• 2007

The Viterbi decoder, which employs the maximum likelihood decoding method, is a critical component in forward error correction for digital communication system. However, lowering power consumption on the Viterbi decoder is a difficult task since the number of paths calculated equals the number of distinctive states of the decoder and the Viterbi decoder utilizes trace-back method. In this paper, we propose a method which minimizes the number of operations performed on the comparator, deployed in the SPEC-T Viterbi decoder implementation. The proposed comparator was applied to the ACSU(Add-Compare-Select Unit) and MPMSU(Minimum Path Metric Search Unit) modules on the decoder. The proposed ACS scheme and MPMS scheme shows reduced power consumption by 10.7% and 11.5% each, compared to the conventional schemes. When compared to the SPEC-T schemes, the proposed ACS and MPMS schemes show 6% and 1.5% less power consumption. In both of the above experiments, the threshold value of 26 was applied.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.339-342
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• 1999

무선 환경에서는 한정된 주파수 자원과 소비전력을 고려하여 시스템을 설계하여야 한다. 이와 같은 조건을 만족하는 모뎀기술이 Trellis Coded Modulation(TCM) 방식이다. TCM의 복호 알고리즘으로는 확률적인 최적의 경로추적 알고리즘인 Viterbi 복호 알고리즘을 적용한다. 본 논문에서는 오디오 데이타의 무선전송을 위한 무선모뎀시스템의 수신단에 필요한 Viterbi 디코더를 설계하였다. 설계된 Viterbi 디코더는 고음질의 2채널 무선 오디오 신호(705,6kbps) 처리를 목적으로 하였다. 수신된 데이터에 8-level soft decision을 적용하였다. ACS(Add Compare Select)부와 TB(Traceback) 메모리 블럭은 데이터의 고속처리를 위해 병렬로 설계하였고, traceback depth는 50으로 하였다, 시뮬레이션 결과 설계된 Viterbi 디코더는 1bit, 2bit 등 랜덤하게 발생하는 에러에 대해 정정 능력이 우수하였다.