Browse > Article

A Bit-level ACSU of High Speed Viterbi Decoder  

Kim, Min-Woo (Electronic & Electrical Eng. Dept. Sungkyunkwan University)
Cho, Jun-Dong (Electronic & Electrical Eng. Dept. Sungkyunkwan University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.6, no.4, 2006 , pp. 240-245 More about this Journal
Abstract
Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.
Keywords
Viterbi decoder; ACSU; M-step look ahead; minimized method;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Je-Hyuk Ryu and Jun-Dong Cho, 'Low Power Systolic Array Viterbi Decoder Implementation with a Clock-gating Method,' Vol. 12-A No. 1, Korea Information Processing Society, pp. 1-6, Feb 2005   과학기술학회마을   DOI
2 G.C.Clark, Jr. and J.B. Cain, Error-Correction for Digital Communication. New York : Pleum, 1981
3 V. S. Gierenz, O.Weiss, T. G. Noll, I. Carew, J. Ashley, and R. Karabed, 'A 550 Mb/s radix-4 bit-level pipelined 16-state 0.25-_m CMOS Viterbi decoder,' Proc. IEEE Int. Conf. Application-Specific Systems,Architectures, and Processors, pp. 195？201, 2000   DOI
4 G. Fettweis and H. Meyr, 'A 100 Mbit/s Viterbi decoder chip: Novel architecture and its realization,' Proc. IEEE Int. Conf. Commun   DOI
5 P. J. Black and T. H.-Y. Meng, 'A 1-Gb/s, four-state,sliding block Viterbi decoder,' IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 797-805, June 1997   DOI   ScienceOn
6 G.Fettweis and H.Meyr, 'Feedforward architecture for parallel Viterbi decoding,' J.VLSI Signal Processing, vol.3, pp.105-119, 1991   DOI
7 G.Fettweis, H.Dawid, and H.Meyr,'Minimized method Viterbi decoding: 600 Mb/s per chip,' proc. GLOBECOM 90, vol.3, pp.1712-1716, Dec. 1990   DOI
8 A. J. Viterbi, 'Error bounds for convolutional coding and an asymptotically optimum decoding algorithm,' IEEE Trans. Inform. Theory, vol.IT-13, pp. 260-269, Apr. 1967   DOI   ScienceOn
9 G.Fettweis, H.Meyr, ' High rate Viterbi processor : A Systolic array solution,' IEEE J.SAC, Oct. 1990   DOI   ScienceOn