• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.11-20
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• 1998

Fault simulatior has been used to compute exact fault coverages of test vectors for digial circuits. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP is very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but needs vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors for a few sequential circuits. In this paper, it is shown that the inaccuracy is due to uninitializble flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM is an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.932-933
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• 2015

This paper presents methods to achieve and control accurate output voltage. PSR removed secondary output voltage sensing circuit, therefore standby power loss can be decreased. When sensing the auxiliary winding voltage, sensing must be done at accurate branch which has $V_O$ information. For this reason this paper presents the PSR sensing technique using sawtooth wave and peak detector. Circuit verification carried out with Spectre in Cadence corporation and Manga/Hynix $0.35{\mu}m$ 700V process.

• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.282-284
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• 1999

This paper presents an accurate algorithm for fault location of a single phase to earth fault on a two-parallel transmission line using only one-terminal data. It is impossible to calculate the accurate fault distance, because of the unknown fault resistance and fault current at the fault point. The faulted line circuit and the zero-sequence circuit of two-parallel line are used as a fault location model, which the source impedance of the remote end is not involved. The algorithm can eliminate the effect of load flow and the fault resistance in calculating the fault location.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.13-21
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• 2011

In this paper, the CMOS programmable interface circuit for MEMS gyroscope is presented, and evaluated with the MEMS sensing element. The circuit includes the front-end charge amplifier with 10 bit programmable capacitor arrays, 9 bit DAC for accurate offset calibration, and 10 bit PGA for accurate gain calibration. The self oscillation loop with automatic gain control operates properly. The offset error and gain error after calibration are measured to be 0.36 %FSO and 0.19 %FSO, respectively. The noise equivalent resolution and bias instability are measured to be 0.016 deg/sec and 0.012 deg/sec, respectively. The calibration capability of this circuit can reduce the variations of the output offset and gain, and this can enhance the manufacturability and can improve the yield.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1434-1441
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• 1999

This paper presents an equivalent circuit of the hairpin line filter for accurate analysis and design. Its validity was verified by computer simulations and filter design experiments. Though the various design equations for a hairpin line filter have been proposed, there has not been a practically simplified equivalent circuit because it is hard to effectively represent interconnection effects between non-adjacent elements. In this paper, all the open ports of the hairpin line filter circuit are changed to the short ports using circuit duality, and the resulting circuits are transformed to graph model. The further simplified circuit model is obtained from boundary conditions, and then the final equivalent circuit of the hairpin line filter is derived in a dual structure of the filter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.377-387
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• 2012

An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.12
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• pp.147-155
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• 2010

We studied on performance improvement of TTM(TI21 Test Meter) that is test and diagnosis devices for jointless audio frequency track circuit on Korean electric railway TI21 standard. Upgraded devices is AD-TTM(Advanced TI21 Test Meter). This can measure alternating frequency USB(Upper signal band) and LSB(Lower signal band). In the audio frequency track circuit, ${\pm}17[Hz]$ of nominal frequency are demodulated and supplied to track relay through AND gate. It is important that measurement function which is error between USB and LSB. Need of AD-TTM will stand out in the electric railway system because this is simple and accurate rather than the former device.

• Structural Engineering and Mechanics
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• v.62 no.6
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• pp.675-693
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• 2017

In this paper, based on the first-order shear deformation plate theory, buckling analysis of piezoelectric coupled transversely isotropic rectangular plates is investigated. By assuming the transverse distribution of electric potential to be a combination of a parabolic and a linear function of thickness coordinate, the equilibrium equations for buckling analysis of plate with surface bonded piezoelectric layers are established. The Maxwell's equation and all boundary conditions including the conditions on the top and bottom surfaces of the plate for closed and open circuited are satisfied. The analytical solution is obtained for Levy type of boundary conditions. The accurate buckling load of laminated plate is presented for both open and closed circuit conditions. From the numerical results it is found that, the critical buckling load for open circuit is more than that of closed circuit in all boundary and loading conditions. Furthermore, the critical buckling loads and the buckling mode number increase by increasing the thickness of piezoelectric layers for both open and closed circuit conditions.