• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.1202-1208
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• 1995

Inter-processor communication is required to manage resources in ATM switching system where processors are distributed. ATM switching system, which was developed in our institute, does't have dedicated communication path for inter-processor communication, but use the ordinary switching network same as user data. Therefore, we should test communication paths and equipments before running various application software programs. In this paper, we propose a method to test communication paths between processors in ATM switching system and describe an implemented program using this method.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1845-1857
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• 1996

An alarm gathering interface equipment has been developed to collect the hardware failure activities in 1$1, 024\times1, 024$ ATM switching system. The equipment use 8-bit microprocessor and ELA-232C port, and is fabricated in a single board, which called Alarm Gathering Interface board Assembly(AGIA). It is programmed to ensure flexibility in modification and expansion of the system capability. The performance is successfully proved through communication test with hardware blocks or modules consisting a ATM switching system, these techniques can be used to develop operation and maintenance functions for more superior ATM switching system in the near future. we additionally have presented some items for further study on alarm subsystem often ATM switching system.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.229-232
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• 1998

Modern telecommunications are increasingly demanding the addition of complex switching features to switching system software. These improvements also should satisfy customer demands for quick provisioning of new service features. But whenever we have developed the switching system in various types, we met problems that are lack of system engineers and short developments terms. We need new guidelines of software design to meet the demands and overcome our problems. So we propose new software platform, scenario driven call control engine (SDCCE) for ATM switching system software and implement an effective call control software using scenarios for ATM Switching System. A scenario is a set of procedures and supplementary scenarios written in data structure and gives benefits to easy adapt new or modified function by adding a scenario. The goal of SDCCE is to increase reusability and readability of software. Especially, it gives a good software extensibility and maintainability. And when we developed ptmp call processing control software, we could get high productivity by reusing scenarios and procedures of ptp call processing control software. We applied the scenario driven call control software to ATM switching system.

• Journal of the Korea Society for Simulation
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• v.6 no.2
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• pp.117-124
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• 1997

A simulation model for the estimation of cutoff connection rate in the asynchronous transfer mode (ATM) switching system under multimedia traffic environments is presented. The simulator is developed by the integration of the AweSim tool with user-written C++ routines that model the internal structures of operational details of the switching system. For the case study, the simulator is applied to the ATM switching system developed by Electronics and Telecommunications Research Institute (ETRI) to compare design alternatives according to the cutoff connection rates.

• Journal of Korean Institute of Industrial Engineers
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• v.19 no.1
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• pp.47-59
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• 1993

Recently, Broadband ISDN(B-ISDN) has received increased attention as a communication architecture which can support multimedia applications. Also, Asynchronous Transfer Mode(ATM) is considered as a promising technique to transfer and switch various kinds of media, such as telephone speech, data and motion video. Comparisons among a variety of ATM switching systems which have already been proposed will provide quite useful information for the new ATM switching system design. To facilitate the comparison, we introduce the design requirements and classification criteria for the ATM switch, and propose a performance analysis model for the Banyan network which is the basic switching fabric of most multi-stage ATM switching systems. The model is based on the standard discrete-time Markov chain analysis and can be conveniently used for extensive Banyan network analysis. The computational results are also presented.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.277-280
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• 1998

As user's demands for high-speed data traffic are recently increased, ABR services are considered as one of important service requirements in ATM networks. Unfortunately, a number of existing ATM switching systems have structural drawbacks as to support ABR services because these switching systems have been developed to support realtime(rt) services such as CBR and rt-VBR services. To support ABR services in the existing ATM switching systems, new traffic control mechanisms for ABR services are required. This paper proposes a method for supporting ABR services in ATM swithcing systems without back-pressure mechanisms and evaluates the performance of the proposed method using simulation.

• Journal of Korea Society of Industrial Information Systems
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• v.4 no.3
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• pp.44-51
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• 1999

This paper presents the queuing model for evaluating the performance of TMN EMS with ATM switching systems. TMS for managing ATM switching systems has a hierarchical structure that consists of managers at the top level, agents at the middle, and ATM switching systems at bottom. A manager communicates with several agents, and an agent manages an ATM switching system We define a queuing model in order to predict the capacity and performance for managers in EMS. By evaluating the queuing model, we can predict the average service time and capacity of EMS.

• ETRI Journal
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• v.18 no.3
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• pp.107-125
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• 1996

In this paper, we define the general requirements of ATM switching systems such as scalability, distributed fashion, and modularity. Also we propose a practical implementation of a scalable ATM switching system whose capacity can be easily expanded. Firstly, the architecture of the system is discussed with an emphasis on system scalability, modularity of subsystems and the simple control network of the design requirements. Secondly, we suggest the three types of distributed call/connection control schemes that are suitable for our switching system. We also estimate their call processing capacity on the average and make a comparison of them under the various system architectures. Since our scalable switching system can be constructed to perform the call processing functions on the various levels of the system capacity, it has much adaptability at the various evolution phases or regions of the network environment.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.947-960
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• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• ETRI Journal
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• v.17 no.1
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• pp.23-36
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• 1995

We present a performance evaluation model of cell reassembly mechanism in an ATM switching system. An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications network. In such a system, there should be interface to convert inter-processor communication traffic from message format to cell format and vice versa, that is, mechanisms to perform the segmentation and reassembly sublayer. In this paper, we employ a continuous-time Markov chain for the performance evaluation model of cell reassembly mechanism with individual buffering, judicially defining the states of the mechanism. Performance measures such as message loss probability and average reassembly delay are obtained in closed forms. Some numerical illustrations are given for the performance analysis and dimensioning of the cell reassembly mechanism.