• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.327-334
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• 2001

네트워크를 설계하고 서비스를 구현하는데 있어서 중요한 변수중의 하나는 트래픽의 특성을 파악하는 것이다. 기존의 트래픽 예측과 분석은 포아송(Poisson) 또는 마코비안(Markovian)을 기본으로 하는 모델을 사용하였다. LAN, WAN 및 VBR(Variable Bit Rate) 트래픽 특성에 관한 최근의 실험적 연구들은 기존의 포아송 가정에 의한 모델들이 네트워크 트래픽의 장기간 의존성 및 self-similar 특성들을 과소평가 함으로써 실제 트래픽의 특성을 제대로 나타낼 수 없다는 것을 지적해 왔다. 따라서 최근 실제 트래픽 모델과 유사한 모델로서 self-similarity 특성을 이용한 접근법이 대두되고 있다. 본 논문에서는 self-similarity 트래픽의 정의에 대해서 논한다. 그리고 실제 트래픽을 수집하고, 인위적으로 self-similarity한 트래픽과 포아송 모델을 적용시킨 트래픽을 발생시켜 비교한 다음 ATM 스위치의 큐(Queue)에 적용하였다. 본 논문에서는 ATM 스위치의 큐에 self-similarity 트래픽을 적용했을 경우 low bound상에서 버퍼 오버플로우 확률 및 셀 손실 확률에 대해 평가하였다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2484-2496
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• 2000

High speed switches have been developing to interconnect a large number of nodes. It is important to analyze the switch performance under various conditions to satisfy the requirements. Queueing analysis, in general, has the intrinsic problem of large state space dimension and complex computation. In fact, The petri net is a graphical and mathematical model. It is suitable for various applications, in particular, manufacturing systems. It can deal with parallelism, concurrence, deadlock avoidance, and asynchronism. Currently it has been applied to the performance of computer networks and protocol verifications. This paper presents a framework for modeling and analyzing ATM switch using stochastic activity networks (SANs). In this paper, we provide the ATM switch model using SANs to extend easily and an approximate analysis method to apply A TM switch models, which significantly reduce the complexity of the model solution. Cell arrival process in output-buffered Queueing A TM switch with finite buffer is modeled as Markov Modulated Poisson Process (MMPP), which is able to accurately represent real traffic and capture the characteristics of bursty traffic. We analyze the performance of the switch in terms of cell-loss ratio (CLR), mean Queue length and mean delay time. We show that the SAN model is very useful in A TM switch model in that the gates have the capability of implementing of scheduling algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10e
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• pp.85-87
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• 2002

본 논문은 SNMP(Simple Network Management Protocol)기반의 ATM 교환 장비를 CMIP(common management information protocol)기반의 관리망에 연동하기 위한 Q3 Adaptor 기능 중 ATM 연결 관리와 Frame Relay 연동 관리를 소개한다. 본 논문의 ATM연결 관리는 점대점(Point-to-Point Permanent Virtual Connection) PVC(P)로 한정하고, FR 연동 관리는 ATM/FR 연결의 One-to-One PVC로 한정하며 ATM 밀 ATM/FR 연결에 대하여 CMIP Manager, Q3 Adaptor 및 교환 장비의 DB간 불일치 현상을 극복하기 위한 현행화 기능도 소개한다.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.463-470
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• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1756-1764
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• 1996

In this paper, we propose a new switch element of buffered Banyan network and analysis it. The proposed switch element consists of CASO(Content ASsociated Output) buffers, its controller and 2*2 crossbar switch. This switch element increase the performance of buffered Banyan network by removing HOL blocking. Also, we analyze the proposed switch element by mathematical modelling method based on MY analysis model which is one of earier proposed models.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.27-33
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• 2003

This paper proposes the efficient audit method for the distributed connection information in ATM switch. Based on this method, we design the periodic audit function by a system and immediate audit function by a operator's order. We evaluate the performance about the proposed Audit method. At the result of evaluation, We figure out that the load of call control processor is almost independent of a system load regardless of audit function operation. Therefore, we confirm that the proposed audit method nearly have an effect on the load of call control processor. The proposed audit method can reestablish a Mismatched connection information with a little load.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.1-9
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• 1998

ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.122-131
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• 2000

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

• The KIPS Transactions:PartC
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• v.8C no.2
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• pp.164-172
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• 2001

최근 인터넷의 확산과 더불어 디지털 비디오 라이브러리(DVL : Digital Video Library) 서비스에 대한 관심이 고조되고 있다. 그러나 현재의 통신망 대역폭과 스위칭 환경 하에서는 종단간 QoS 보장하는데 많은 제약사항이 존재한다. 따라서 본 논문에서는 비디오 스트림 처리를 효율적으로 수행하여, 지연-처리율 특성을 만족할 수 있는 스트림 스위칭 구조를 제안하고 이에 대한 성능을 분석하였다. 제안된 ATM-기반 스트림 스위치는 각각 다중화되는 CBR(Constant Bit Rate) 및 VBR(Variable Bit Rate) 스트림의 QoS(Quality of Service)를 보장해야만 한다. 성능분석 결과는 제안된 스위치의 처리율이 r=4일 때 약 0.996의 값을 보였으며, 지연시간도 부하가 0.7 이하일 때 2미만으로 특정되었다. 이 결과는 제안된 구조가 적당한 입력 스트림의 그룹핑을 통하여 비디오 응용을 위한 처리율 및 지연 요구사항 QoS를 보장할 수 있음을 보여준다.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.319-326
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• 2001

본 논문에서는 다단계상호연결 네트워크에 기반한 입력버퍼 구조의 ATM 스위치에 관해서 언급한다. 제안된 방법은 HOL 블록킹으로 인해 균일 트래픽(uniform traffic) 하에서 최대 약 58.6%의 처리율을 넘지 못하는 문제를 해결 할 수 있는 방법을 제시하며, 또한 오류허용 기능을 확장시키기 위하여 베이스라인 네트워크에서 버디 연결 매핑 및 제한연결 매핑 특성을 이용한 다중경로를 제공할 수 있는 버퍼 기법에 관하여 언급한다. 시뮬레이션에 의한 성능 평가 결과, 기존 방식과 비교하여 좋은 처리율과 셀 손실율을 보였으며, 더욱이 오류 스위치의 증가에도 불구하고 처리율의 수준은 적정한 셀 지연 범위 내에서 유지될 수 있음을 보여주고 있다.