• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.132-138
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• 1998

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR, ABR) generated by a wide range of services. The traffic ABR uses the remined space of the CBR/VBR traffics bandwith. The Rate-based, the Credit-based, and the mixed method that are implementing the control loop of ABR traffic service is on study. In this paper, a new algorithm that can be considered in ATM and effectively manage ABR traffic using VS/VD method and EPRCA algorithm is proposed on the switch of the Rate-based method

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.8
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• pp.1190-1200
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• 1993

In this work, the performance of both delay sensitive traffics and loss sensitive traffics of the output buffered ATM switch with priority control mechanisms has been evaluated. We choose the partial buffer sharing mechanism as the loss priority control mechanism and the HOL(Head Of Line) priority control mechanism as the time priority control mechanism. We model loss sensitive traffics with Poisson process and delay sensitive traffics with MMPP. With loss priority control, it is confirmed that loss probability of loss sensitive traffice decreases when the loss priority control mechanism is chosen. With time priority control, it has also been confirmed that mean cell delay of delay sensitive traffics decreases when the HOL priority control mechanism is used. From this analysis, It has been confirmed that the requirements of QOS for both loss sensitive and delay sensitive traffics can be satisfied in the ATM switch by combining both the loss priority control mechanism and the HOL priority control mechanism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.122-131
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• 2000

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.437-445
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• 2000

More advanced and demanding applications, like videoconferencing, video on demand. distributed computing etc., have been devised thanks to the availability of enhanced network feature. Network technologies need to be enhanced to support these applications and to cope with the increasing number of users. Increasing the availability of network resources is just not enough to achieve this goal; scalable network architecture. increased packet forwarding capabilities, a wider range of services are all additional requirements. MOLS (multiprotocol label Switching) is one of the new networking techniques under standardization in the scientific community. In this paper, we analyze the performance of label switching in ATM networks. Simulation tests were performed. In this simulation, we set a simple network configuration and used internet traffic traces from NLANR as input traffic sources. The simulation results and analysis will be helpful in utilizing the functions of ATM switching and IP routing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1393-1398
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• 2003

In this paper, we propose a new switch architecture with one schedule at k-time slots, which k means the allocated time slots for each schedule. A conventional switch system uses a single time slot per each schedule but the proposed switch system uses multiple time slots per each schedule. Both the conventional switch md the proposed switch have same throughput but our switch system occupies multiple cell time slots per each schedule and hence can be implemented in scheduler of simple circuitry compared to the conventional switch. The proposed scheduling method for switch system will be applicable in switch system with high-speed data link rate.

• The Journal of the Korea Contents Association
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• v.4 no.4
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• pp.189-196
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• 2004

Most of the recent researches for ATM switches have been based on multistage interconnection network known as regularity and self-routing property. These networks can switch packets simultaneously and in parallel. However, they are blocking networks in the sense that packet is capable of collision with each other Mainly Banyan network have been used for structure. There are several ways to reduce the blocking or to increase the throughput of banyan-type switches: increasing the internal link speeds, placing buffers in each switching node, using multiple path, distributing the load evenly in front of the banyan network and so on. Therefore, this paper proposes the use of recirculating shuffle-exchange network to reduce the blocking and to improve hardware complexity. This structures are recirculating shuffle-exchange network as simplified in hardware complexity and Rank network with tree structure which send only a packet with highest priority to the next network, and recirculate the others to the previous network. after it decides priority number on the Packets transferred to the same destination, The transferred Packets into banyan network use the function of self routing through decomposition and composition algorithm and all they arrive at final destinations. To analyze throughput, waiting time and packet loss ratio according to the size of buffer, the probabilities are modeled by a binomial distribution of packet arrival. If it is 50 percentage of load, the size of buffer is more than 15. It means the acceptable packet loss ratio. Therefore, this paper simplify the hardware complexity as use of recirculating shuffle-exchange network instead of bitonic sorter.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.273-276
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• 1998

This paper proposes a new Asynchronous Transfer Mode(ATM) switch architecture for the Broadband ISDN. The proposed switch has the architecture to prohibit the out-of-sequence in shared buffer switch system with being fixed buffer size in the out-buffered large scale ATM Switch System. then in this paper proposes cell resequence algorithm to decrease the out-of-sequence problem. also, we studied the out-of-sequence problem that was occurred by the cell transfer delay and the cell overflow due to the fixed buffer size when cell resequenced and we propose to implement optimal ACFIFO(Address Counter First In First Out) buffer size which has the minimized cell loss.

• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.1-8
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• 1999

This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.405-407
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• 1999

WFQ(Weighted Fair Queuing)은 지연이나 공평성의 특성에 있어서 이상적인 트래픽 스케줄링 알고리즘으로 간주되었다. N세션에 서비스를 제공하는 WFQ 스케줄러의 스케줄링 연산은 각 패킷 전송 시간당 O(n)의 계산 복잡도를 가지며, 구현 또한 복잡하다. Self-Clocked Fair Queuing과 같은 WFQ 알고리즘의 구현을 간단히 하고자 하는 노력은 지연범위나 특성에 영향을 주게 되어 다양한 트래픽이 제공되는 경우 각 트래픽의 공평성을 지원해주지 못한다. 그러므로 지연이나 지연 변이 측면에서 공평성을 지원하고 구현상의 계산 복잡도를 줄인 스케줄링 알고리즘이 필요하게 되었다. ATM 다중화기의 셀 스케줄링 알고리즘 역시, ATM의 특성상 다양한 특성의 서비스를 제공하기 위해서, 다양한 특성의 트래픽에 대한 공평성을 제공하는 새로운 알고리즘의 연구가 필요하다. 이 논문에서는 ATM 스위치 내의 다중화기에서 사용되는 새로운 셀 스케줄링 알고리즘을 제안하고 실험을 통해 이 알고리즘의 성능을 검증하고자 한다. 이 알고리즘은 여러 개의 우선 순위 큐를 갖고, 각 우선순위 큐마다 스케줄링 연산이 O(1)의 계산 복잡도를 갖는 Parallel Priority Queuing 알고리즘이다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1781-1787
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• 1997

Future high speed networks are expected to use the Asynchronous Transfer Mode(ATM), which provides desired quality of service for the various traffic types(e.g., voice, video and data). Proper traffic control scheme helps ensure efficient and fair operation of networks. In this paper, we analyze various related traffic-control strategies and propose a new traffic control scheme and ATM control architecture with an integrated buffer management method and multi-thresholds in order to solve the problem of each class's cell loss ratio and cell delay in ATM networks. In addition, we evaluate the performance improvement of the proposed traffic control scheme through simulation. As shown in the result, the proposed traffic control scheme improves cell loss ratio in proportion to the buffer size.