• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1646-1655
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• 1999

This thesis presents a new VHDL intermediate format CDDG(Control Dominated Data Graph) and a minimal constrained scheduling algorithm for an optimal control dominated ASIC design. CDDG is a control flow graph which represents conditional branches and loops efficiently. Also it represents data dependency and such constraints as hardware resource and timing. In the proposed scheduling algorithm, the constraints using the inclusion and overlap relation among subgraphs. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• Electronics and Telecommunications Trends
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• v.3 no.1
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• pp.24-42
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• 1988

최근 시스템 설계를 위해 크게 각광받고 있는 ASIC 설계기술에 대한 정의 및 흐름에 대하여 기술하였으며, 특히 최근의 동향으로서 인터페이스 부문, 테스트 용이화 설계, 고급언어와 실리콘 컴파일러, H/W엔진 개발의 동향 등에 관하여 한 subject씩 구체적인 설명을 하였다.

• The Journal of Korean Association of Computer Education
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• v.16 no.3
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• pp.99-105
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• 2013

The FPGA-based emulation is an essential step in ASIC design for validation. For emulation with maximal frequency, it is crucial to understand the FPGA characteristics. This paper attempts to analyze the performance characteristics of the modern FPGAs from renowned vendors, Xilinx and Altera, with a case study utilizing various adders and MIPS CPU. Unlike the common wisdom, ripple-carry adder (RCA) does not utilize the inherent carry-chain inside FPGAs when structurally designed based on 1-bit adders. Thus, the RCA shows the inferior performance to the other types of adders in FPGAs. Our study also reveals that FPGAs from Xilinx exhibit different characteristics from the ones from Altera. That is, the prefix adder, which is optimized for speed in ASIC design, shows the poor performance on Xilinx devices, whereas it provides a comparable speed to the IP core on Altera devices. It suggests that error-prone manual change of the original design can be avoided on Altera devices if area is permitted. Experiments with MIPS CPU confirm the arguments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.929-935
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• 2003

An analog/digital mixed mode ASIC for network synchronization of ATM switching system has been designed and fabricated. This ASIC generates a 234.7/46.94 ㎒ system clock and 77.76/19.44 ㎒ user clock using 46.94 ㎒ transmitted clocks from other systems. It also includes digital circuits for checking and selecting of the transmitted clocks. For effective ASIC design, full custom technique is used in 2 analog PLL circuits design, and standard cell based technique is used in digital circuit design. Resistors and capacitors for analog circuits are specially designed which can be fabricated in general CMOS technology, so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology with no expensive. Testing results show stable 234.7 ㎒ and 19.44 ㎒ clocks generation with each 4㎰ and 17㎰ of low ms jitter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of IKEEE
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• v.23 no.3
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• pp.947-953
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• 2019

The purpose of this paper is to explore an ASIC design for estimating sizes and concentrations of airborne micro-particles by the means of integrating, amplifying and digitizing electric charge signals generated by photo-sensors as it receives scattered photons by the presence of micro-particles, consisting of a pre-amplifier that detects and amplifies voltage or current signal from photo-sensor that generates charges (hole-electron pairs) when exposed to visible rays, infrared rays, ultraviolet rays, etc. according to the intensity of rays; a shaper for shaping the amplified signal to a semi-gaussian waveform; two discriminators and binary counters for outputting digital signals by comparing the magnitude of the shaped signal with an arbitrary reference voltages. The ASIC with the proposed architecture and functional blocks in this study was designed with a 0.18um standard CMOS technology from Global Foundries and the operation and performances of the ASIC has been verified by the silicons fabricated by using the process.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.605-609
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• 2000

This paper presents a development of the Pulse Width Modulation ASIC for control of the AC servo or spindle motor in machine tools. The ASIC is designed two PWM functions for simultaneous control of a converter and an inverter. Also the device includes additionally two UART functions for interfacing the RS232C with PC or other devices. The device is connected to the microprocessor of Intel or Motorola by bus interface. The required output voltage and frequency for the motor control is programmed to the PWM block and the corresponding switching signals are calculated and generated with regard to the programmed value.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2758-2760
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• 1999

ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.166-176
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• 1995

This paper presents a new high-level synthesizer for ASIC designs using ASIC library or FPGAs. DAMUL defines the VHDL description for a specified hardware and allocate some VHDL codes, which describe the behavioral specification, to the corresponding hardware before the synthesis. The interconnections are implemented by the multiplexers, and the objective of allocation is the minimization of the number of multiplexers. Also, the dedicated registers is used for global variables, in order to implement the other necessary registers as well as status and control registers. The effectiveness of the proposed system is shown by the synthesis results of benchmark circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.798-804
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• 2003

In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.