• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.69-77
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• 2002

In this paper, we present the CDMA2000 1x compliant mobile station modem chip (SCom5010) implemented in a 0.18${\mu}{\textrm}{m}$ CMOS technology.[1] ARM940T cached processor. TeakLite DSP core, and other peripheral blocks are integrated with the baseband modem chip. Also we show novel verification methodologies and explain how this chip can be used as an emulation processor.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1733-1736
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• 2005

본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.649-651
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• 2012

본 논문에서는 Core-A를 이용한 실시간 영상 신호 처리 SoC 설계와 검증에 대해 기술한다. 영상 신호 처리를 위한 방식으로 SoC를 사용하였으며 영상 처리를 위한 ISP를 설계하였다. 영상 처리를 위한 마이크로프로세서는 코드밀도를 높이고 Verilog HDL을 사용하여 기술되어 여러 응용분야에서 최적화할 수 있는 국내에서 개발된 Core-A를 사용하였다. 본 논문에서 제안한 SoC는 Verilog HDL언어로 설계 되었고, 기본 SoC의 구조는 Core-A, AMBA Bus, ISP, Memory controller, Uart로 구성하였다. 구현된 SoC는 다양한 영상 신호 처리를 지원하여 향후 영상압축 인코더의 실시간 이미지 처리용 소스로 사용할 수 있고 신호 처리 알고리즘 검증용에도 유용하게 사용될 수 있을 것으로 보인다. 설계 검증을 위해 먼저 FPGA를 이용하여 검증하였으며 TSMC $0.18{\mu}m$ CMOS공정으로 합성한 결과 동작주파수는 50MHz, 전체 게이트 수 86.1k로 확인되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.212-218
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• 2012

A stereo vision is able to build three-dimensional maps of its environment. It can provide much more complete information than a 2D image based vision but has to process, at least, that much more data. In the past decade, real-time stereo has become a reality. Some solutions are based on reconfigurable hardware and others rely on specialized hardware. However, they are designed for their own specific applications and are difficult to extend their functionalities. This paper describes a vision system based on a System on a Chip (SoC) platform. A real-time stereo image correlator is implemented using Sum of Absolute Difference (SAD) algorithm and is integrated into the vision system using AMBA bus protocol. Since the system is designed on a pre-verified platform it can be easily extended in its functionality increasing design productivity. Simulation results show that the vision system is suitable for various real-time applications.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.59-62
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• 2003

The purpose of this paper is to present how to implement Segment_LCD display using SoC design. The SoC design is achieved by using an ARM_based Excalibur device. The Excalibur device offers an outstanding embedded development platform with ARM922T and FPA. The design in the Excailbur device uses the embedded AR띤 Processor core and the AMBA high-performance bus (AHH) to write to a memory-mapped slave peripheral in the FPGA portion of the device. Here, Segment_LCD is one kind of memory-mapped slave peripherals. In order to Implement the Segment_LCD display based on SoC design, four steps are fellowed. At first, IP modules are made by using Verilog HDL. Secondly, the ARM processor of the Excalibur is programmed using C in ADS (ARM Developer Suite). And in the third step, the whole system is simulated and verified. At last, modules are downloaded to SoCMaster kit. Both Quartus II software and ModelSim5.5e software are the key software tools during the design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.