• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2045-2049
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• 2008

In this paper, we propose an novel architecture for H.264 High Profile Encoder Intra Prediction module. This designed module can be operated in 306 cycle for one-macroblock. To verify the Encoder architecture, we developed the reference C from JM 13.2 and verified the our developed hardware using test vector generated by reference C. We adopt plan removal and SAD calculation to reduce the Hardware cost and cycle. The designed circuit can be operated in 133MHz clock system, and has 250K gate counts using TSMC 0.18 um process including SRAM memory.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.1525-1527
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• 2013

본 논문에서는 저시력자의 개선된 독서 환경을 제공하는 시각보조기기를 위한 실시간 영상처리 SoC(System on Chip) 하드웨어 구조 설계에 대해서 기술한다. 기존의 시각보조기기는 화면 영상이 실제 움직임보다 늦게 출력되는 잔상 현상이 발생하며, 색 변환 기능도 제한적이다. 따라서 본 논문에서 제안하는 실시간 영상처리 SoC 하드웨어 구조는 데이터 연산을 최소화함으로써 잔상 현상이 감소되며, 저시력자를 위한 다양한 색상 모드를 지원한다. 제안하는 영상처리 SoC 하드웨어 구조는 Core-A 모듈, Memory Controller 모듈, AMBA AHB bus 모듈, ISP(Image Signal Processing) 모듈, TFT-LCD Controller 모듈, VGA Controller 모듈, CIS Controller 모듈, UART 모듈, Block Memory 모듈로 구성된다. 시각보조기기를 위한 실시간 영상처리 SoC 하드웨어 구조는 Virtex4 XC4VLX80 FPGA 디바이스를 이용하여 검증하였으며, TSMC 180nm 셀 라이브러리로 합성한 결과 동작주파수는 54MHz, 게이트 수 197k이다.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.105-116
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• 2008

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.80-86
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• 2010

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus priority is primarily considered. In this paper, we propose the arbitration method that calculates the bus utilization of each master. Furthermore, we verify the performance compared with the other arbitration methods through TLM(Transaction Level Model). From the results of performance verification, the arbitration methods of Fixed Priority and Round-Robin can not set the bus utilization and those of TDMA and Lottery happen the error of 50% and 70% respectively compared with bus utilization set by user in more than 100,000 cycles. On the other hand, the bandwidth-award bus arbitration method remains the error of less than 1% since approximately 1000 cycles, compared with bus utilization set by user.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.86-93
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• 2010

A system-on-chip (SoC) includes more functions and requires rapidly increased data bandwidth as the development of semiconductor process technology and SoC design methodology. As a result, the data bandwidth of on-chip-networks in SoCs becomes a key factor of the system performance, and the research on the on-chip-network is performed actively. Either AXI or OCP is considered to a substitute of the AHB which has been the most popular on-chip-network. However, they have much increased number of signal wires, which make it difficult to design the interface logic and the network hardware. The compatibility of the protocols with other protocols is not so good. In this paper, we propose a new interface protocol for on-chip-networks to improve the problems mentioned above. The proposed protocol uses less number of signal wires than that of the AHB and considers the compatibility with other interface protocols such as the AXI. According the analysis results, the performance of the proposed protocol per wire is much better than that of the AXI although the absolute performance is slightly inferior.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.15-21
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• 2008

Several shared buses are divided hierarchically and connected with a bridge in the bus topology that consists of many components such as SoCs. Because the bridge topology is capable of the simultaneous communication of components in the several buses, the bus performance has improved definitely. However, when the inter-bus data transaction happens, the latency increases seriously in the bridge block. In this paper, a variety of bridge architectures are analyzed in the point of view of merit and demerit. Superior frying bridge topology is proposed in the aspects of performance, IP reusability, timing margin, gate count and circuit complexity. In contrast with the conventional bridge that has only a role to switch the inter-bus data, the frying bridge can communicate directly between the bus and the slave, which decreases the traffic overhead of a shared bus and improves the performance of a bridge communication.

• Proceedings of the Korean Society of Near Infrared Spectroscopy Conference
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• 2001.06a
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• pp.1126-1126
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• 2001

The paper presented here is the initial part of a larger study, in which it was determined which quality parameters in cheese powder could already be predicted by NIR at an early stage in the process and which could only be predicted at the final stages of the process. This initial study was performed in order to establish the levels and nature of variation within and between batches such that the subsequent data collection could be tackled optimally. The perspectives evolved into more than was originally planned and revealed some interesting uses of NIR-technology. Cheese powder production starts as a batch process, where waste cheese from other dairies is melted down in a vat. The process then turns into a continual process as the vat is emptied and the melted cheese is then filtered, homogenized, pasteurized and finally spray dried. Between each batch the powder is to a greater or lesser degree a mixture of 2 batches. This paper is divided into 2 aspects, one regarding the optimization of sampling time and the other is a study of process dynamics. Optimizing sampling time This initial study included 9 powder samples from 9 different batches produced during one day. The raw materials for the batches were chosen with the aim of creating a relatively high level of variation in the data. The total of 81 samples were taken out at regular intervals and spectra were collected on a NIR-systems 6500 instrument. The subsequent reduction of the data by PCA to score values shows the power of NIR as a tool to determine not only when samples are representative of a certain batch, but also which batches are stable enough to include in a further study. Studying process dynamics To take this experiment a step further 1 of the 81 samples were sent to the laboratory for further analyses. The samples were chosen on the criteria that they covered the spectral variation in the dataset. These samples were analysed for 4 chemical components and 5 physical attributes, which are essential for describing the quality of the product. The latent structure of the 7 samples, using the chemical and physical variables, is totally comparable to the latent structure of the NIR spectra. This outcome makes it possible to describe the dynamics of one day's production both chemically and physically with relatively little resources. Additionally it raises the question as to whether reference values are needed, as the latent structure of the NIR-spectra appears to be sufficient in providing information on the quality of the product. To be able to use NIR in this way would require defining quality limits in the principal component space as opposed to each of the reference values. The potential of NIR applied in an explorative fashion with batch processes opens a whole new gateway for the use of this technology. This study explains yet again after so many years in the field “why I'm crazy about NIR!”.