• Journal of IKEEE
• /
• v.13 no.1
• /
• pp.41-48
• /
• 2009

This paper describes an implementation of the analog front end (AFE) incorporated with the image signal processing (ISP) unit in the SoC, dominating the performance of the CCD image sensor system. New schemes are exploited in the high-frequency sampling to reduce the sampling uncertainty apparently as the frequency increases, in the structure for the wide-range variable gain amplifier (VGA) capable of $0{\sim}36\;dB$ exponential gain control to meet the needed bandwidth and accuracy by adopting a new parasitic insensitive capacitor array. Moreover, the double cancellation of the black-level noise was efficiently achieved both in the analog and the digital domain. The proposed topology fabricated in a $0.35-{\mu}m$ CMOS process was proved in a full CCD camera system of 10-bit accuracy, dissipating 80 mA at 15 MHz with a 3.3 V supply voltage.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.4
• /
• pp.2217-2224
• /
• 2014

This paper deals with system development which measures 12 channel ECG using medical analog front end(AFE) and discriminates arrythmia through signal analysis. Recently, occurrences of cardiac arrest have been increased. So the need of system that diagnoses an arrythmia which results in cardiac arrest is increasing. There are some drawbacks of conventional 12 channel ECG system that it occupies bulk and consists of complicated circuit. To improve those, we made up the system composed of medical AFE, algorithm for discriminating arrythmia and DSP for signal processing. This system can be monitored 12 channel ECG waveforms and the discriminant analysis result of arrhythmia through 7" LCD and received the input through touch pannel. In this study, we conducted normal operation test about output signal of ECG simulator(normal/abnormal ECG signal) to verify the implemented system and performance evaluation of the optimization process for applying arrhythmia algorithm to an embedded environment.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.129-140
• /
• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• Journal of the Semiconductor & Display Technology
• /
• v.14 no.2
• /
• pp.67-72
• /
• 2015

For the development of UFS device test system, M-PHY specifications should be matched with MIPI-standard which is analog signal protocol. In this paper, the implementation methodology and hardware structure for the M-PHY AFE (Analog Front End) Block was suggested that it can be implemented using universal components without ASIC process. The testing procedure has a jitter problem so to solve the problems we using ASIC process, normally but the ASIC process needs a lot of developing cost making the UFS device test system. In is paper, the suggestion was verified by the output signal which was compared to the MIPI-standard on the Prototype-board using universal components. The board was reduced the jitter on the condition of HS-TX and 5.824 Gbps Mode in SerDes (Serialize-deserializer). Finally, the suggestion and developed AFE block have a useful better than ASIC process on developing costs of the industrial UFS device test system.

• Journal of IKEEE
• /
• v.14 no.1
• /
• pp.8-16
• /
• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1141-1144
• /
• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• Journal of IKEEE
• /
• v.15 no.4
• /
• pp.324-329
• /
• 2011

In recent years, the performance and functions of portable devices has increased. so it requires more power efficiency and energy density while using the battery for a long time. therefore Battery pack which are made up from several battery cells in series in order to achieve higher operating voltage is being used. when using a Li-ion battery, we need a protection circuit to protect from overcharge, over discharge, high temperature and over current. Also, when using battery pack, we need to Cell voltage balancing circuit that each cell in tune with the balancing. In this paper, the proposed IC is applicable by mobile devices as well as E-bike, hybrid vehicles, electric vehicles, and is expected to contribute to the development of domestic PMIC.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.5
• /
• pp.579-587
• /
• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.12C
• /
• pp.1282-1287
• /
• 2002

In this Paper, we present the design of 10Mbps HomePNA(Home Phoneline Networking Alliance) PHY which is Home Network Technology using phone-line. It is connected with external interface through MII(Media Independent Interface) and AFE(Analog Front End) Interface. 10Mbps HomePNA PHY is composed with Management Block IEEE 802.3 CSMA/CD MAC(Media Access Control) Block Modulator block and Demodulator block. For their verification, we designed a prototype FPGA PCB board using XPC860T made in Motorola. We verified HomePNA frame data transmission using a driver program based Linux kernel. we verified rate negotiation by HomepNA 2.0 Link Layer Protocol.

• Information and Communications Magazine
• /
• v.14 no.3
• /
• pp.75-86
• /
• 1997

This manuscript describes the high level system design for the DCP system. The DCP HS and BS transceivers are composed of five systems, including the RF/IF unit, the Analog Front End(AFE), the baseband modem, the voice codec and the micro-controller. In the following, the core transceiver architecture with the primary functions at these subsystem is described.