• Title/Summary/Keyword: AES-CCM*

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Considering Barrier Overhead in Parallelizing AES-CCM (동기화 오버헤드를 고려한 AES-CCM의 병렬 처리)

  • Chung, Yong-Wha;Kim, Sang-Choon
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.21 no.3
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    • pp.3-9
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    • 2011
  • In this paper, we propose workload partitioning methods in parallelizing AES-CCM which is proposed as the wireless encryption and message integrity standard IEEE 802.11i. In parallelizing AES-CCM having data dependency, synchronizations among processors are required, and multi-core processors have a very large range of synchronization performance. We propose and compare the performance of various workload partitioning methods by considering both the computational characteristics of AES-CCM and the synchronization overhead.

Design of Low-Complexity 128-Bit AES-CCM* IP for IEEE 802.15.4-Compatible WPAN Devices (IEEE 802.15.4 호환 WPAN 기기를 위한 낮은 복잡도를 갖는128-bit AES-CCM* IP 설계)

  • Choi, Injun;Lee, Jong-Yeol;Kim, Ji-Hoon
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.45-51
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    • 2015
  • Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

Research on the Implementation of the AES-CCM Security Mode in a High Data-Rate Modem (고속 모뎀에서의 AES-CCM 보안 모드 구현에 관한 연구)

  • Lee, Hyeon-Seok;Park, Sung-Kwon
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.60 no.4
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    • pp.262-266
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    • 2011
  • In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

Efficient FPGA Implementation of AES-CCM for IEEE 1609.2 Vehicle Communications Security

  • Jeong, Chanbok;Kim, Youngmin
    • IEIE Transactions on Smart Processing and Computing
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    • v.6 no.2
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    • pp.133-139
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    • 2017
  • Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

Area-Optimized Multi-Standard AES-CCM Security Engine for IEEE 802.15.4 / 802.15.6

  • Choi, Injun;Kim, Ji-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.3
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    • pp.293-299
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    • 2016
  • Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

Implementation and Analysis Performance of CCM, GCM based ARIA Block CIpher for Korea CMVP. (KCMVP를 위한 MICOM 환경에서의 ARIA-CCM, ARIA-GCM 구현 및 성능분석 비교)

  • Lee, Jae-Hoon;Park, Minha;Hwang, Nu-Ri;Yi, Okyeon;Kim, Kiheon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.05a
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    • pp.267-270
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    • 2014
  • As Smart Device research processes, the needs of information security in light devices is increasing. For example, Zigbee provide Information Security by applying $AES-CCM^*$ defined IEEE 802.15.4 standard. However, according to information security law in Korea, only devices with KCMVP certification can be used in government organization and facilities. Therefore, this paper provide a solution to apply ARIA-CCM and ARIA-GCM for KCMVP in reserved field of IEEE 802.15.4 standard. For analyzing performance, we provide the speed test result of ARIA-CCM and ARIA-GCM comparing with $AES-CCM^*$.

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The Efficient AES-CCM Architecture for a hardware library in the WAVE (WAVE 하드웨어 암호 라이브러리에 적합한 효율적인 AES-CCM 구조 설계)

  • Lee, Yeon-Cheol;Seo, Hwa-Jeong;Kim, Ho-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.12
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    • pp.2899-2905
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    • 2013
  • According to developing wireless communications in vehicle, various security threat in the WAVE(Wireless access in vehicular environments) is increased. To protect this, IEEE 1609.2 specify services as for prevent message from attacks such as spoofing, eavesdropping and replay. It is possible to implement a hardware library for defending these attacks. In this paper, we proposed a efficient AES-CCM architecture for the hardware library in the WAVE. We compare our architecture to the previous one in the same FPGA. And our design uses less slices than 27 % of it and less slices than 45 % of it if we share registers that were used by other modules in the library. We also achieves a throughput of 1355 Gbits/s in xc5vlx110t-2ff1136.

A Design of Authentication/Security Processor IP for Wireless USB (무선 USB 인증/보안용 프로세서 IP 설계)

  • Yang, Hyun-Chang;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.11
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    • pp.2031-2038
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    • 2008
  • A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

An Efficient Hardware Implementation of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security (IEEE 802.11i 보안용 AES 기반 CCM 프로토콜의 효율적인 하드웨어로 구현)

  • Hwang, Seok-Ki;Lee, Jin-Woo;Kim, Chay-Hyeun;Song, You-Su;Shin, Kyung-Wook
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.591-594
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    • 2005
  • This paper describes a design of AES-based CCM Protocol for IEEE 802.11i Wireless LAN Security. The CCMP core is designed with 128-bit data path and iterative structyre which uses 1 clock cycle per round operation. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 23% compared with conventional LUT-based design. The CCMP core designed in Verilog-HDL has 35,013 gates, and the estimated throughput is about 768Mbps at 66-MHz clock frequency.

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A Design of AES-based WiBro Security Processor (AES 기반 와이브로 보안 프로세서 설계)

  • Kim, Jong-Hwan;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.7 s.361
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    • pp.71-80
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    • 2007
  • This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.