• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.335-337
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• 1993

Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.293-294
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• 2006

The conventional strain measuring device is costly and complicated - it is not simple to understand its structure. Hence, strain gage and the A/D converter are assembled to come up with a load and a strain measuring device. The device was tested for measuring the strain in a loaded specimen and the experimental results were compared to those obtained by a commercial strain indicator.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.571-572
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• 2008

We propose a 4-bit 1.6GSample/s flash-A/D converter realized in a digital 0.18um 1-poly 4-metal CMOS technology. To achieve low power with good performance, we employ immanent C2MOS comparator scheme. The kickback noise is one of the most important issue in A/D comparator performance. To decrease the effect of kickback noise, here we introduce kickback neutralization technique. The designed A/D converter has an effective number of bits(ENOBs) of 3.93 while using 32mW operating at 1.6GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.153-156
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• 2001

This paper describes a 12-bit high speed pipeline CMOS A/D converter. The A/D converter simulated the 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. The results show DNL and INL of $\pm$0.5LSB and $\pm$1.0LSB, conversion rate of 100Msamples/s, and power dissipation of 500㎽ with a power supply of 3.3V

• 대한전자공학회논문지
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• 제8권5호
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• pp.1-9
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• 1971

양산화를 전제로한 계수형계측기로서 4자리표시, 정도 ±0.1% 진치 ±1 digit 이내, 입력 impedance 1000MΩ 이상(1.500V 범위), 측정범위 1mV∼1,000V 4단절환, 자동영점교정으로 저항 및 직류전류 측정기능도 갖춘 Digital Voltmeter를 목표로 이에 적합한 A/D 변환기를 추구하였다. 이 결과 A/D 변환기에서 일어나는 적분 slope의 직선성에 미치는 요인을 해석하여 매우 간단한 회로구성으로도 효과적인 성능을 보장 할 수 있음을 확인하였다.

• Journal of Power Electronics
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• 제17권1호
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• pp.41-55
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• 2017

This study proposes a novel zero voltage transition (ZVT) pulse width modulation (PWM) DC-DC interleaved boost converter with an active snubber cell. All the semiconductor devices in the converter turn on and off with soft switching to reduce the switching power losses and improve the overall efficiency. Through the interleaved approach, the current stresses of the main devices and the ripple of the output voltage and input current are reduced. The main switches turn on with ZVT and turn off with zero voltage switching (ZVS). The auxiliary switch turns on with zero current switching (ZCS) and turns off with ZVS. In addition, the snubber cell does not create additional current or voltage stress on the main switches and main diodes. The proposed converter can smoothly achieve soft switching characteristics even under light load conditions. The theoretical analysis and operating stages of the proposed converter are made for the D > 50% and D < 50% modes. Finally, a prototype of the proposed converter is implemented, and the experimental results are given in detail for 500 W and 50 kHz. The overall efficiency of the proposed converter reached 95.5% at nominal output power.

• 한국정보통신학회논문지
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• 제9권5호
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• pp.1073-1081
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• 2005

본 논문은 상위 7비트와 하위 3비트의 segmented 전류원 구조로서 최적화 된 binary-thermal decoding 방식을 이용한 3.3v 10비트 CMOS D/A 변환기를 제안한다. segmeted 전류원 구조와 최적화 된 binary-thermal decoding 방식을 D/A 변환기가 지니므로 가질 수 있는 장점은 디코딩 논리회로의 복잡성을 단순화함으로 칩면적을 줄일 수 있다. 제안된 변환기는 0.35um CMOS n-well 표준공정을 이용하여 제작되었으며, 유효 칩면적은 $0.953mm^2$ 이다. 설계된 칩의 상승/하강시간, 정작시간 및 INL/DNL은 각각 1.92/2.1 ns, 12.71 ns, ${\pm}2.3/{\pm}0.58$ LSB로 나타났다. 또한 설계된 D/A 변환기는 3.3V의 공급전원에서는 224mW의 전력소모가 측정되었다.

• Journal of Power Electronics
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• 제14권4호
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• pp.641-648
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• 2014

This paper presents the design considerations and analysis for an interleaved boundary conduction mode power factor correction buck converter. A thorough analysis of the harmonic content of the AC line current is presented to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing efficiency. The results of the harmonic analysis are used to derive the required value of K and therefore the output voltage necessary to meet the class D requirements for a given AC line voltage. The discussed design consideration and harmonic current analysis are verified on a 300W universal line experimental prototype converter with an 80V output. The measured efficiencies remain above 96% down to 20% of the full load. The input current harmonics also meet the IEC61000-3-2 (class D) standard.

• 전자공학회논문지
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• 제50권11호
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• pp.64-69
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• 2013

본 논문에서는 10-bit 해상도의 Two-Step Single-Slope A/D 변환기를 이용한 고속 CMOS Image Sensor(CIS)를 제안하였다. 제안하는 A/D 변환기는 5-bit coarse ADC 와 6-bit fine ADC 로 구성되어 있으며, 기존의 Single-Slope A/D 변환기보다 10배 이상의 변환속도를 나타내었다. 또한 고속 동작에서 적은 노이즈 특성을 갖기 위해 Digital Correlated Double Sampling(D-CDS) 회로를 제안하였다. 설계된 A/D 변환기는 0.13um 1-poly 4-metal CIS 공정으로 제작되었으며 QVGA($320{\times}240$)급 해상도를 갖는다. 제작된 칩의 유효면적은 $5mm{\times}3mm$ 이며 3.3V 전원전압에서 약 35mW의 전력소모를 나타내었다. 변환속도는 10us 이었으며, 프레임율은 220 frames/s으로 측정되었다.

• 전기학회논문지
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• 제66권9호
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• pp.1341-1350
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• 2017

In this paper, a high reliability 30W DC-DC converter is designed considering military standard (MIL-STD) for military applications such as guided weapon and aircraft. The performances and specifications of conventional military grade DC-DC converter are practically analyzed. The requirements for military grade DC-DC converter are established in consideration of MIL-STD and analysis results of conventional product. Two isolated DC-DC converter, forward and fly-back converter, are designed and compared to determine topology. From experimental results under various operating conditions, the forward topology satisfied performances and specifications of MIL-STD for military DC-DC converter.