• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.3
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• pp.208-216
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• 2018

In this paper, an LLC resonant converter employing two coupled inductors on the secondary side of the converter is proposed. The conventional LLC converter exhibits serious power loss during secondary winding of the transformer because of generation of tremendous output current ripples. To overcome this problem, an LLC resonant converter with a current doubler as a rectifying circuit was recently proposed. However, the current-doubler rectifying circuit requires coupled inductors with a high coupling ratio to retain the designed resonance characteristics. Therefore, an additional hardware filter is required at the output stage to address large output current ripples. Additional design procedures are also necessary because the inductance component of the added filter affects the designed resonant network. To solve this issue, an LLC resonant converter employing two coupled inductors is proposed in this paper. Mathematical analysis shows that the proposed secondary-side current-doubler circuit does not affect the designed resonance characteristics. The operating principles and theoretical analyses are proven through a simulation and experiments with a 54 V/28 A prototype.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.18-27
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• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.857-860
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• 1991

This paper describes a High-Speed 8-bit Current-Mode BiCMOS A/D Converter. The characteristics of this A/D Converter are as fellows. First, as ADC is operating in current-mode we can obtain the properties of increase of converting speed, low noise, and wideband. Second, the properties of high switching speed in bipolar transistor and of high packing density, low power consumption in MOS trnsistor are combined. Finally we reduce chip area by designing it with subranging mode and improve the converting speed by performing subtraction directly, which doesn't need D/A convertings, using current switching element. This converter is composed of two 4-bit ADC, current soure array which provides signal and reference current, current comparator and encoding network.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1573-1576
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• 1987

A 4-bit parallel-series A/D converter has been designed using a new matrix circuit and breadboarded with transister array(TPQ2483). The simple matrix circuit is substituted for D/A converter and sebtracter-multiplier. The system has been simulated with SPICE. This converter is capable of operating at clock rate of 20MHz.

• Journal of Power Electronics
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• v.10 no.5
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• pp.461-467
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• 2010

This paper proposes a new soft-switched Sepic converter. It has low switching losses and low conduction losses due to its auxiliary communicated circuit and synchronous rectifier operation, respectively. Because of its positive and buck/boost-like DC voltage transfer function (M=D/(1-D)), the proposed converter is desirable for use in distributed power systems. The proposed converter has versions both with and without a transformer. The paper also suggests some design guidelines in terms of the power circuit and the control loop for the proposed converter.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.129-134
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• 2014

This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.