• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.2
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• pp.724-737
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• 2020

Corrected Block TEA(or XXTEA) is a block cipher designed to correct security weakness in the original block TEA in 1998. In this paper, XXTEA cipher hardware which can encrypt or decrypt between 64-bit and 256-bit messages using 128-bit master key is implemented. Minimum message block size is 64-bit wide and maximal message block size is 256-bit wide. The designed XXTEA can encrypt and decrypt variable-length message blocks which are some arbitrary multiple of 32 bits in message block sizes. XXTEA core of this paper is described using Verilog-HDL and downloaded on Vertex4. The operation frequency is 177MHz. The maximum throughput for 64-bit message blocks is 174Mbps and that of 256-bit message blocks is 467Mbps. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.23-32
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• 1998

In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.235-238
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• 2002

This paper presents a way of a novel FPGA implementation of DCT. It shows how to limit the required bits on each DCT processing step, instead of implementing high-cost 64-bit floating-point arithmetic of IEEE Std 754-1985 on FPGA. ID-DCT implementation has been done which operates at 30 frame per second with 1920${\times}$1080 resolution.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.600-616
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• 2021

SIMON and SPECK are two families of lightweight block ciphers that have excellent performance on hardware and software platforms. At CRYPTO 2019, Gohr first introduces the differential cryptanalysis based deep learning on round-reduced SPECK32/64, and finally reduces the remaining security of 11-round SPECK32/64 to roughly 38 bits. In this paper, we are committed to evaluating the safety of SIMON cipher under the neural differential cryptanalysis. We firstly prove theoretically that SIMON is a non-Markov cipher, which means that the results based on conventional differential cryptanalysis may be inaccurate. Then we train a residual neural network to get the 7-, 8-, 9-round neural distinguishers for SIMON32/64. To prove the effectiveness for our distinguishers, we perform the distinguishing attack and key-recovery attack against 15-round SIMON32/64. The results show that the real ciphertexts can be distinguished from random ciphertexts with a probability close to 1 only by 2^8.7 chosen-plaintext pairs. For the key-recovery attack, the correct key was recovered with a success rate of 23%, and the data complexity and computation complexity are as low as 2⁸ and 2^20.1 respectively. All the results are better than the existing literature. Furthermore, we briefly discussed the effect of different residual network structures on the training results of neural distinguishers. It is hoped that our findings will provide some reference for future research.

• The Journal of the Acoustical Society of Korea
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• v.14 no.2E
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• pp.50-56
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• 1995

This paper describes an efficient coding method for Korean characters using a three-state transition graph. To our knowledge, this is the first achievement of its kind. This new method, called the Paralle Hangul Dynamic Coding Method(PHDCM), compresses about 3.5 bits per a Korean character, which is more than 1 bit shorter than the conventional codes introduced thus far to achieve extensive code compression. When we ran the method on a MasPar machine, which is on SIMD SM (EFEW-PRAM)., it achieved a 49.314-fold speedup with 64 processors having 10 million Korean characters.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.32-39
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• 1989

This paper presents Lucifer-type encryption algorythms with variable length of block size of 32, 64, and 256 bits by varying the key byte access schedule and the unfolded convolution register of Lucifer. The intersymbol dpendence and exhaustive cryptanalysis of the algorithms are examined and compared. We also present the methods which improve the intersymbol dependence such as moving the location of key interruption and autoclave selection of S-box.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1019-1024
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• 2006

A system design and realization for real time DVR system with robust video watermarking algorithm for contents security is presented in this paper. The robust video watermarking is used the intraframe space region and interframe insertion simultaneously, and to be processed at real time on image data and algorithm is used the 64bits special purpose quad DSP processor with assembly and soft pipeline codes. The experimental result shows that the processing time takes about 2.5ms in the D1 image per frame for 60% moving image.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1994.11a
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• pp.29-31
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• 1994

In digital signature schemes derived from the zero-knowledge proof techniques, some authors often claims that the length of hash-values for their schemes could be as short as 64 or 72 bits for the security level of 2$^{-64}$ or 2$^{-72}$ . This letter shows that signature schemes with such short hash values cannot achieve the security levels as stated, due to the birthday attack by the signer.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.274-280
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• 2011

Due to their rapid growth and new paradigm applications, wireless sensor networks(WSNs) are morphing into low power personal area networks(LoWPANs), which are envisioned to grow radically. The fragmentation and reassembly of IP data packet is one of the most important function in the 6LoWPAN based communication between Internet and wireless sensor network. However, since the 6LoWPAN data unit size is 102 byte for IPv6 MTU size is 1200 byte, it increases the number of fragmentation and reassembly. In order to reduce the number of fragmentation and reassembly, this paper presents a new scheme that can be applicable to 6LoWPAN. When a fragmented packet header is constructed, we can have more space for data. This is because we use 8-bits routing table ill instead of 16-bits or 54-bits MAC address to decide the destination node. Analysis shows that our design has roughly 7% or 22% less transmission number of fragmented packets, depending on MAC address size(16-bits or 54-bits), compared with the previously proposed scheme in RFC4944. The reduced fragmented packet transmission means a low power consumption since the packet transmission is the very high power function in wireless sensor networks. Therefore the presented fragmented transmission scheme is well suited for low-power wireless sensor networks.