FPGA를 이용한 HDTV인코더를 위한 DCT회로의 구현

DCT Implementation on FPGA for HDTV Encoder

This paper presents a way of a novel FPGA implementation of DCT. It shows how to limit the required bits on each DCT processing step, instead of implementing high-cost 64-bit floating-point arithmetic of IEEE Std 754-1985 on FPGA. ID-DCT implementation has been done which operates at 30 frame per second with 1920${\times}$1080 resolution.