• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.10
• /
• pp.67-75
• /
• 1998

This paper examined the geometrical variables of microstrip to control the characteristic impedance of MCM interconnect and also with respect to the practical requirements, evaluated the critical lengths for attenuation, propagation delay, and crosstalk at 500 MHz frequency compared to at 50 MHz frequency. With the illustration of each MCM-L and MCM-D interconnect having 50 characteristic impedance, it was revealed that the most important geometrical variables to control the characteristic impedance of microstrip are eventually dielectric thickness and line width. In particular, the dielectric thickness of MCM-D interconnect must be controlled with tolerance below 2 m. It is clear that the attenuation does not give rise to signal distortion in the range of up to 500MHz frequency for both MCM-L and MCM-D interconnects. However, the propagation delay is so significant that both MCM-L and MCM-D interconnects should be matched with load at the 500 MHz frequency. For the MCM-D interconnect, the crosstalk voltage would not be high to generate the wrong signal on the neighboring line at 500 MHz frequency, but the MCM-L interconnect could not be used due to severe crosstalk. Eventually, it is clear that the transmission line behavior must be studied for the design of MCM substrate at the 500 MHz frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.5
• /
• pp.312-320
• /
• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.485-487
• /
• 2006

This paper describes a frequency synthesizer designed in a $0.25{\mu}m$ CMOS technology for using local oscillators for the IF stages. The design is focused mainly on low-power characteristics. A simple ring-oscillator based VCO is used, where a single control signal can be used for variable resistors. The designed PLL includes all building blocks for elimination of external components, other than the crystal, and its operating frequency can be programmed by external data. It operates in the frequency range of 250MHz to 800MHz and consumes l.08mA at 500MHz from a 2.5V supply. The measured phase noise is -85dBc/Hz in-band and -105dBc/Hz at 1MHz offset. The die area is $1.09mm^2$

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.699-702
• /
• 1998

This paper presents a 500MHz 1.1㎱ 32kb synchronous CMOS SRAM macro using $0.35\mu\textrm{m}$ CMOS technology. In order to operate at high frequency and reduce power dissipation, the designed SRAM macro is realized with optimized decoder, multi-point sense amplifier(MPSA), selective precharge scheme and etc. Optimized decorder and MPSA respectively reduce 50% and 40% of delay time. Also, a selective precharge scheme reduces 80% of power dissipation in that part.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.11
• /
• pp.1259-1268
• /
• 2010

In this paper, we presented a new LC prototype synthesis method for the multi-band filter. For synthesis a multi-band filter with the required frequency response, we proposed the diagram of poles and zeros, also, we proposed the optimization process for finding the combination of optimized poles and zeros. From the transfer and reflection functions calculated from poles and zeros, we performed the quasi-elliptic LC prototype synthesis of multi-band filter. Using the proposed LC prototype synthesis method of multi-band filter, dual-band filter operating at GSM(880~960 MHz) and ISM(2,400~2,500 MHz) and triple-band filter operating at GSM(880~960 MHz) and ISM(2,400~2,500, 5,725~5,850 MHz) were designed and fabricated.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2006.07a
• /
• pp.378-378
• /
• 2006

• The KIPS Transactions:PartA
• /
• v.10A no.3
• /
• pp.247-254
• /
• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.6
• /
• pp.619-627
• /
• 2014

In this paper, we designed a blade antenna for VHF-UHF band(500 MHz~3 GHz) to be used as aircraft antennas. Unlike previously reported researches that use high-dielectric materials and insert rectangular extended grounds, the antenna structure was designed by optimizing the curvature of both a radiator and an extended ground whose shape is varied by changing the exponent of an n-th polynomial. Based on the optimized structure, we measured impedance matching and gain performances to evaluate the antenna in the VHF-UHF band(500 MHz~3 GHz). As a result, we confirmed that the antenna shows matching characteristics of less than -6 dB and has average gains of greater than -5 dBi in the entire VHF-UHF band.

• Proceedings of the KIEE Conference
• /
• 2011.07a
• /
• pp.1676-1677
• /
• 2011

본논문에서는 300MHz~500MHz대역에서 -80dBm~-30dBm의 레벨로 발생하는 초고압 전력기기의 부분방전을 감지 할 수 있는 RF 모듈에 적용 가능한 LNA와 믹서를 설계하였다. 모니터링이 가능하도록 시스템 버짓을 실시하고, 설계된 부품들을 하나의 모듈로 합쳐 시뮬레이션 함으로써, 시스템의 목표에 맞게 설계 되었음을 확인하였다. LNA와 필터, 두단의 믹서를 통해 BPF로 가는 헤테로다인 방식을 사용하였으며 이중 설계된 가장 첫 단의 LNA와 주파수 합성 역할을 하는 첫 단 믹서를 다른 이상적인 소자들과 함께 시뮬레이션 하였으며, 그 결과 300MHz~500MHz대역에서 가변이득증폭기의 가변이득 폭이 14dB ~ 56dB까지 변할 때 출력신호가 20MHz에서 3 ~ 5dBm으로 일정하게 나오는 것을 확인하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.4
• /
• pp.377-387
• /
• 2016

Design of X-band frequency FMCW based imaging radar with multi-resolutions and performances of the self-manufactured radar system are presented in this study. In order to implement the multi-bandwidths, a ramp sequence of the FMCW signal is consisting of two kinds of 'saw-tooth' waveform with different bandwidth, and a receiver circuit consisting of L-band source and frequency converter circuit is used to effectively extract spectra of beat-frequency from the received signal of X-band frequency. The system setups for performance measurement of self-manufactured radar system are maximum output power of 35 dBm, sampling frequency of 1.2 MHz and sweep time of 1 ms. Then, the measured resolutions of the modulated signal having bandwidth of 500 MHz and 300 MHz in range & azimuth-direction are (0.28 m, 0.26 m) and (0.44 m, 0.27 m), respectively.