• ETRI Journal
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• v.30 no.2
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• pp.261-267
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• 2008

In this paper, we propose and demonstrate a cost-effective technique to upgrade the capacity of dense wavelength division multiplexing (DWDM) networks to a 40 Gb/s line rate using the existing 10 Gb/s-based infrastructure. To accommodate 40 Gb/s over the link optimized for 10 Gb/s, we propose applying a combination of super-FEC, carrier-suppressed return-to-zero, and pre-emphasis to the 40 Gb/s transponder. The transmission of 40 Gb/s DWDM channels over existing 10 Gb/s line-rate long-haul DWDM links, including $40{\times}40$ Gb/s transmission over KT's standard single-mode fiber optimized for 10 Gb/s achieves successful results. The proposed upgrading technique allows the Q-value margin for a 40 Gb/s line rate to be compatible with that of 10 Gb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4B
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• pp.637-646
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• 2010

For 40 Gb/s data transmission through electrical backplane trace up to 40 inch length on four layer fire-resistant (FR-4), we have designed the 40 Gb/s backplane channel model consisting of four channel 10 Gb/s. Simulation results show an enhancement of backplane channel characteristics excellent more than requirements specified in IEEE P802.3ba at 10 Gb/s. This paper provides a review of the structures and algorithms used in receive and adaptive equalization for 40 Gb/s backplane Ethernet. The use of this backplane channel model could achieves better receive equalizer at great data rate than 10 Gb/s.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.134-139
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• 2004

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of pre-amplifiers, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2B
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• pp.197-209
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• 2010

In this paper, We have designed and analyzed a characteristics of backplane channel having 40 inch strip line length of four lanes and Flame Retardant four (PR-4) material, and have designed 40 Gb/s Receive and adaptive equalizer and its high-speed equalization algorithm using the backplane channel characteristics. For 40 Gb/s high-speed data communications pass through the backplane, a 10Gb/s 4 channel receive & equalizer with DFE except for FFE was proposed. This receive and equalizer meets the requirements of the IEEE Std P802.3ba standard-based receive equalizer to implement equalizers on the receive end of a 46 inch length's backplane channel.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.136-139
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• 2003

A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of signal amplifiers, a nonlinear circuit with diodes, and a bandpass filter Before implementing the 40 Gb/s clock recovery circuit, a 10 Gb/s clock recovery circuit has been successfully implemented and tested. With the 40 Gb/s clock recovery circuit, when a 40 Gb/s NRZ signal of -10 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -20 dBm output power after passing through the nonlinear circuit. The output signal from the nonlinear circuit passes through a narrow-band filter, and then amplified. The implemented clock recovery circuit is planned to be used for the input of a phase locked loop to further stabilize the recovered clock signal and to reduce the clock jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5B
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• pp.809-815
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• 2010

This paper proposes the structures and algorithms for the adaptive equalizer that are required to allow high speed signaling over 40 Gb/s across a backplane channel. The proposed adaptive DFE has a fast convergence and low computational complexity. Simulations with a 40 Gb/s show that our adaptive equalizer can meet the IEEE 802.3ba requirement for backplane strip line up to 40 inches.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.438-441
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• 2003

본 논문은 10Gb/s 클라이언트 신호를 4 채널까지 매핑 및 다중화하여 40Gb/s OTN 신호를 생성하는 OTU3 프레이머의 구조 설계를 기술한다. 클라이언트 신호는 상호 비동기인 경우 먼저 ODU2 로 비트 동기식으로 매핑된 후 ODU3 페이로드에 자리맞춤 방법으로 매핑 및 다중화될 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• ETRI Journal
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• v.30 no.2
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• pp.268-274
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• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.