• 한국세라믹학회지
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• 제41권3호
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• pp.216-220
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• 2004

본 논문은 압전세라믹의 압전상수 d$_{33}$ 를 이용한 적층 세라믹 박판 작동층 IDEAL (InterDigitated Electrode Actuation Layer)의 개발에 관한 것이다. 대부분의 박판 압전 작동층은 압전상수 d$_{31}$ 효과를 이용하고 있다. 현재 개발된 압전작동기의 성능을 향상시키기 위해 많은 연구가 수행 중에 있으며, 그 중 한 방법이 압전상수 d$_{33}$ 를 이용하는 방법이다. 압전세라믹의 압전상수 d$_{33}$ 는 압전상수 d$_{31}$ 보다 일반적으로 두배 정도이기 때문에 d$_{33}$ 작동 효과를 활용하면 작동기의 성능을 향상시킬 수 있다. 미국 MIT에서 개발된 AFC와 NASA Langley 연구소 연구팀이 개발한 LaRC-MFC$^{TM}$는 d$_{33}$ 작동 효과를 활용하였으나 빗살형 전극이 작동층 상하 표면에 부착되어 있어 완전한 d$_{33}$ 작동 효과를 활용하였다고 볼 수 없다. 본 논문에서는 빗살형 전극을 세라믹 층간에 삽입한 적층형 세라믹 박판 작동층을 설계하고 제작하였다. 제작된 작동층의 작동 스트레인을 측정하였고 LaRC-MFC$^{TM}$의 작동 스트레인과 비교한 결과, 본 연구에서 개발한 박판 세라믹 작동층이 15% 이상의 작동 스트레인을 발생시킬 수 있음을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• 마이크로전자및패키징학회지
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• 제20권1호
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• pp.7-13
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• 2013

3D 적층 IC 개발을 위한 본딩 기술의 현황에 대해 알아보았다. 실리콘 웨이퍼를 본딩하여 적층한 후 배선 공정을 진행하는 wafer direct bonding 기술보다는 배선 및 금속 범프를 먼저 형성한 후 금속 본딩을 통해 웨이퍼를 적층하는 공정이 주로 연구되고 있다. 일반적인 Cu 열압착 본딩 방식은 높은 온도와 압력을 필요로 하기 때문에 공정온도와 압력을 낮추기 위한 연구가 많이 진행되고 있으며, 그 가운데서 Ar 빔을 조사하여 표면을 활성화 시키는 SAB 방식과 실리콘 산화층과 Cu를 동시에 본딩하는 DBI 방식이 큰 주목을 받고 있다. 국내에서는 Cu 열압착 방식을 이용한 웨이퍼 레벨 적층 기술이 현재 개발 중에 있다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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• pp.225-230
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• 2005

The proposed Triple-band Compact Chip Antenna using Coupled Meander line and stacked meander Structure for Mobile RFID/PCS/WiBro. The proposed antenna is designed to operate at 900, 1800, and 2350 MHz, and is realized by parasitic coupled and stacked a meander line. Meander lines are using extend length of effective current path more than monopole and contribute miniaturization. The coupled meander line controls the excitations of the Mobile RFID and PCS, stacked meander line controls the excitation of the WiBro. The proposed antenna size is $11mm\times22.5mm\times1mm$. The antenna supports 900MHz, 1800MHz and 2350MHz operations simultaneously with bandwidths of 33MHz, 230MHz and 100MHz, respectively. The proposed antenna gains are result of simulation to be -0.8dBi, 3dBi and 3.8dBi, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제4권2호
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• pp.41-46
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• 2015

컴퓨터 사용 환경이 모바일 시장 및 소형 전자기기 시장 등으로 다양해짐에 따라 저전력 고성능 시스템에 대한 요구도 커지고 있다. 3차원 die-stacking 기술은 한정된 공간에서 DRAM의 집적도과 접근 속도를 높여 차세대 공정방식으로 많은 연구가 되고 있다. 이 논문에서는 3차원 구조의 DRAM 로직층에 재구성형 가속기를 구현하여 저전력 고성능 시스템을 구성하는 방법을 제안한다. 또한 재구성형 가속기의 지역 메모리로 캐시를 적용하고 활용하는 방법에 대해서 논의한다. DRAM의 로직층에 재구성형 가속기를 구현할 경우 위치적인 특성으로 데이터 전송 및 관리에 필요한 비용이 줄어들어 성능을 크게 향상시킬 수 있다. 제안된 시스템에서는 최대 24.8의 스피드업을 기록하였다.

• 전기전자학회논문지
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• 제28권2호
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• pp.234-238
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• 2024

본 논문은 낮은 구동 전류 특성과 3차원 적층 구조로 확장시킬 수 있는 장점을 가진 3차원 적층형 이중 팁 RRAM을 CNN 가속기 아키텍처에 접목하는 연구를 수행한 논문이다. 3차원 적층형 이중 팁을 적층 형태의 병렬연결로 시냅스 어레이에 사용하여 멀티-레벨을 구현하였다. 이를 Network-on-chip 형태의 가속기 내에 DAC, ADC, 버퍼 및 레지스터, shift & add 회로 등 다양한 하드웨어 블록들과 함께 구성하여 CNN 가속기에 대한 시뮬레이션을 수행하였다. 시냅스 가중치와 활성화 함수의 양자화는 16-bit으로 가정하였다. 해당 가속기 아키텍처를 위한 병렬 파이프라인을 통해 CNN 연산을 시뮬레이션한 결과, 연산효율은 약 370 GOPs/W를 달성하였으며, 양자화에 의한 정확도 열화는 3 % 이내가 되는 결과를 나타냈다.

• ETRI Journal
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• 제41권3호
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• pp.396-407
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• 2019

Laser-assisted bonding (LAB) is an advanced technology in which a homogenized laser beam is selectively applied to a chip. Previous researches have demonstrated the feasibility of using a single-tier LAB process for 3D through-silicon via (TSV) integration with nonconductive paste (NCP), where each TSV die is bonded one at a time. A collective LAB process, where several TSV dies can be stacked simultaneously, is developed to improve the productivity while maintaining the reliability of the solder joints. A single-tier LAB process for 3D TSV integration with NCP is introduced for two different values of laser power, namely 100 W and 150 W. For the 100 W case, a maximum of three dies can be collectively stacked, whereas for the 150 W case, a total of six tiers can be simultaneously bonded. For the 100 W case, the intermetallic compound microstructure is a typical Cu-Sn phase system, whereas for the 150 W case, it is asymmetrical owing to a thermogradient across the solder joint. The collective LAB process can be realized through proper design of the bonding parameters such as laser power, time, and number of stacked dies.

• 한국초전도ㆍ저온공학회논문지
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• 제24권3호
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• pp.47-51
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• 2022

With the innovative development of bio, pharmaceutical, and semiconductor technologies, it is essential to demand a next-generation transfer system that minimizes dust and vibrations generated during the manufacturing process. In order to develop dust-free and non-contact transfer systems, the high temperature superconductor (HTS) bulks have been applied as a magnet for levitation. However, sintered HTS bulk magnets are limited in their applications due to their relatively low critical current density (J_c) of several kA/cm² and low mechanical properties as a ceramic material. In addition, during cooling to cryogenic temperatures repeatedly, cracks and damage may occur by thermal shock. On the other hand, the bulk magnets made by stacked HTS tapes have various advantages, such as relatively high mechanical properties by alternate stacking of the metal and ceramic layer, high magnetic levitation performance by using coated conductors with high J_c of several MA/cm², consistent superconducting properties, miniaturization, light-weight, etc. In this study, we tried to fabricate HTS tapes stacked bulk magnets with 60 mm × 60 mm area and various numbers of HTS tape stacked layers for magnetic levitation. In order to examine the levitation forces of bulk magnets stacked with HTS tapes from 1 to 16 layers, specialized force measurement apparatus was made and adapted to measure the levitation force. By increasing the number of HTS tapes stacked layers, the levitation force of bulk magnet become larger. 16 HTS tapes stacked bulk magnets show promising levitation force of about 23.5 N, 6.538 kPa at 10 mm of levitated distance from NdFeB permanent magnet.

• 대한의용생체공학회:의공학회지
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• 제31권4호
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• pp.292-301
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• 2010

To restore visual sensation of blind patients, we have proposed a fully implantable retinal prosthesis comprising an three dimensionally (3D) stacked retinal chip for transforming optical signal to electrical signal, a flexible cable with stimulus electrode array for stimulating retina cells, and coupling coils for power transmission. The 3D stacked retinal chip is consisted of several LSI chips such as photodetector, signal processing circuit, and stimulus current generator. They are vertically stacked and electrically connected using 3D integration technology. Our retinal prosthesis has a small size and lightweight with high resolution, therefore it could increase the patients` quality of life (QOL). For realizing the fully implantable retinal prosthesis, we developed a retinal prosthesis module comprising a retinal prosthesis chip and a flexible cable with stimulus electrode array for generating optimal stimulus current. In this study, we used a 2D retinal chip as a prototype retinal prosthesis chip. We fabricated the polymide-based flexible cable of $20{\mu}m$ thickness where 16 channels Pt stimulus electrode array was formed in the cable. Pt electrode has an impedance of $9.9k{\Omega}$ at 400Hz frequency. The retinal prosthesis chip was mounted on the flexible cable by an epoxy and electrically connected by Au wire. The retinal prosthesis chip was cappted by a silicone to pretect from corrosive environments in an eyeball. Then, the fabricated retinal prosthesis module was implanted into an eyeball of a rabbit. We successfully recorded electrically evoked potential (EEP) elicited from the rabbit brain by the current stimulation supplied from the implanted retinal prosthesis module. EEP amplitude was increased linearly with illumination intensity and irradiation time of incident light. The retinal prosthesis chip was well functioned after implanting into the eyeball of the rabbit.