• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.6
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• pp.899-905
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• 2013

In this paper, we focus on how to calibrate multi-cameras easily and how to efficiently detect quad-copters with small-numbered particles. Each particle is a six dimensional vector that is composed of 3D position and 3D orientation of a quad-copter in the space. Due to curse of dimensionality, that leads to explosive computational costs with a large amount of high-dimensioned particles. To detect efficiently, we need to put more particles in very promising spaces and few particles in other spaces. Though computational cost is lowered by minimizing particles, in order to track a quad-copter with multiple cameras in real-time, multiple images from the cameras should be synchronized and analyzed. Therefore, lots of the computations still need to be done. Because of this, GPGPU(General-Purpose computing on Graphics Processing Units) is implemented for parallel computing. This method has been successfully tested and gives accurate results in practical situations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.762-766
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• 2003

In this paper, we present a new approach to solve the problem of estimating the camera 3-D location and orientation from a matched set of 3-D model and 2-D image features. An iterative least-square method is used to solve both rotation and translation simultaneously. Because conventional methods that solved for rotation first and then translation do not provide good solutions, we derive an error equation using roll-pitch-yaw angle to present the rotation matrix. To minimize the error equation, Levenberg-Marquardt algorithm is introduced with uniform sampling strategy of rotation space to avoid stuck in local minimum. Experimental results using real images are presented.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of Environmental Health Sciences
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• v.2 no.1
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• pp.29-31
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• 1975

This experiment Was carried out under two points of view, from May 1st to the end of 1973. One was the comparative determination of the activation factor of Lead dioxide by kinds in measuring of Sulfur oxides concentration by $PbO_2$ cylinder method, and the other was the comparison that result with the record of auto analyzer. Five measuring sites were selected out of Seoul City. Three kinds of Lead dioxide made in Japan (B,C and D) were compared with Standard $PbO_2$ (A for use in Determination of Sulphur in the atmosphere, purity 99% up) made in British Institution, and monthly measuring was conducted at every sampling site. The recording by auto analyzer (Beckman Model 906-A $SO_2$ Analyzer) was conducted once or twice a month for 24 hours at each sampling site during the same period. And some significant results were obtained. 1. In comparative experiments to determine the activation degree of three kinds of Lead dioxide (B,C and D), the obtained correction factor of B reagent was 1.09, 1.16 in C and 1.30 in D against Standard $PbO_2$ (A). Therefore, it should be in need of standardization or clear statement about the reagents for use, in determination sulfur oxides by $PbO_2$ cylinder method. 2. Generally, the concentration of Sulfur dioxide by wilkins' convertion method from $SO_3$ showed about 20-30% higher than those by Auto analyzer.

• Journal of Technology Innovation
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• v.17 no.2
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• pp.1-23
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• 2009

The Survey on the Industrial Research and Development(R&D) is the primary source of information on R&D performed by Korea industrial sector. The results of the survey are used to assess trends in R&D expenditures. Government agencies, corporations, and research organizations use the data to investigate productivity determinants, formulate tax policy, and compare individual company performance with industry averages. Recently, Korea Industrial Technology Association(KOITA) has collected the data by complete enumeration. Koita has, currently, considered sample survey because the number of R&D institutions in industry has been dramatically increased. This study develops survey design for the industrial research and development(R&D) statistics by introducing a sample survey. Companies are divided into 8 groups according to the amount of R&D expenditures and firm size or type. We collect the sample from 24 or 8 sampling strata and compare the results with those of complete enumeration survey. The estimates from 24 sampling strata are not significantly different to the results of complete enumeration survey. We propose the survey design as follows: Companies are divided into 11 groups including the companies of which R&D expenditures are unknown. All large companies are included in the survey and medium and small companies are sampled from 70% and 3%. Simple random sampling (SRS) is applied to the small company partition since they show uniform distribution in R&D expenditures. The independent probability proportionate to size (PPS) sampling procedure may be applied to those companies identified as 'not R&D performers'. When respondents do not provide the requested information, estimates for the missing data are made using imputation algorithms. In the future study, new key variables should be developed in survey questionnaires.

• Food Science of Animal Resources
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• v.21 no.2
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• pp.149-155
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• 2001

The aims of this study were to examine contamination sources and provide the basic data in establishment of sanitary standard for raw pork meat. From \"Random sampling(I)\", initial total plate counts of post-slaughter samples for the group A, B and C were 1.5${\times}10^4$cfu/$textrm{cm}^2$, 5.5${\times}10^5$cfu/$textrm{cm}^2$ and 1.8${\times}10^4$cfu/$textrm{cm}^2$, respectively, and of post-prechilling samples for the group A, B and C were 1.0${\times}10^4$cfu/$textrm{cm}^2$, 4.6${\times}10^5$cfu/$textrm{cm}^2$ and 2.5${\times}10^4$cfu/$textrm{cm}^2$, respectively. Initial total plate counts of post-transportation samples for the group D, E and F did not increased, as did the group A, B and C. From \"Normal sampling(II)\", initial total plate counts of post-slaughter, post-prechilling, post-transportation and post-2 days preservation samples were 7.3${\times}10^4$cfu/$textrm{cm}^2$, 9.6${\times}10^4$cfu/$textrm{cm}^2$, 2.0${\times}10^5$cfu/$textrm{cm}^2$ and 2.5${\times}10^5$cfu/$textrm{cm}^2$, respectively. From \"Clean sampling(III)\", initial total plate counts of post-slaughter, post-prechilling, post-transportation and post-2 days preservation samples were decreased to 7.0${\times}10^2$cfu/$textrm{cm}^2$, 7.5${\times}10^2$cfu/$textrm{cm}^2$, 8.5${\times}10^2$cfu/$textrm{cm}^2$ and 5.5${\times}10^3$cfu/$textrm{cm}^2$, respectively, compared with "Normal sampling(II)". No E. coli O157:H7, Staphylococcus aureus and Salmonella were detected at each sampling step. Consequently, a slaughter method like "Clean sampling(III)" showed a better sanitary effect to low total plate counts of 10$^2$∼10$^3$times, compared with "Normal sampling(II)". The one of contamination sources for raw pork meat was at a slaughtering step, and "Clean sampling" method may be considered as the one of sanitary standards.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.5
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• pp.179-186
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• 2021

For stereo matching based on deep learning, the design of network structure is crucial to the calculation of matching cost, and the time-consuming problem of convolutional neural network in image processing also needs to be solved urgently. In this paper, a method of stereo matching using sparse loss volume in parallax dimension is proposed. A sparse 3D loss volume is constructed by using a wide step length translation of the right view feature map, which reduces the video memory and computing resources required by the 3D convolution module by several times. In order to improve the accuracy of the algorithm, the nonlinear up-sampling of the matching loss in the parallax dimension is carried out by using the method of multi-category output, and the training model is combined with two kinds of loss functions. Compared with the benchmark algorithm, the proposed algorithm not only improves the accuracy but also shortens the running time by about 30%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.69-76
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• 2008

This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.