• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.32-39
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• 1998

This paper presents the experimental results on the 3-electrode DC-PDP which has a common electrode to improve the PDP life cycle. The measured DC characteristic proves the effectiveness of common electrode absorbing about half of discharge currents. The waveforms for pulse memory operation of3-electrode PDP without crosstalk could also be determined from the I-V characteristics. The pulse memory drives of 8*8 cell array show the frequency response fo memory margin and the luminance efficiency of 3-electrode PDP are quite different from genrally known characteristics of 2-electrode DC-PDP.

• ETRI Journal
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• v.45 no.6
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• pp.1035-1045
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• 2023

We propose a novel graphics processing unit (GPU) algorithm that can handle a large-scale 3D fast Fourier transform (i.e., 3D-FFT) problem whose data size is larger than the GPU's memory. A 1D FFT-based 3D-FFT computational approach is used to solve the limited device memory issue. Moreover, to reduce the communication overhead between the CPU and GPU, we propose a 3D data-transposition method that converts the target 1D vector into a contiguous memory layout and improves data transfer efficiency. The transposed data are communicated between the host and device memories efficiently through the pinned buffer and multiple streams. We apply our method to various large-scale benchmarks and compare its performance with the state-of-the-art multicore CPU FFT library (i.e., fastest Fourier transform in the West [FFTW]) and a prior GPU-based 3D-FFT algorithm. Our method achieves a higher performance (up to 2.89 times) than FFTW; it yields more performance gaps as the data size increases. The performance of the prior GPU algorithm decreases considerably in massive-scale problems, whereas our method's performance is stable.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.119-128
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• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• Journal of IKEEE
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• v.25 no.4
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• pp.770-773
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• 2021

In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO₂) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (V_th) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

• Computational Structural Engineering
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• v.4 no.1
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• pp.95-108
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• 1991

An explicit finite element method can be executed more rapidly and effectively on vector computer than on the scalar computer because it has suitable structures for vector processing. In this paper, an efficient vectorization method of the explicit finite element program on the memory-to-memory type vector computer is proposed. First, the general vectorization method which can be applied regardless of the vector architecture is investigated, then the method which is suitable for the memory-to-memory type vector computer is proposed. To illustrate the usefulness of the proposed vectorization method, DYNA3D, the existing explicit finite element program, is migrated on HDS AS/XL V50 which is the memory-to-memory type vector computer. Performance results on actual test show a vector/scalar speedup is above 2.4.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.

• Journal of the Korean Ceramic Society
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• v.37 no.11
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• pp.1084-1090
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• 2000

(Bi$_2$O$_2$)$^{2+}$층 사이에 두 개의 Ta-O 팔면체로 연결된 Bi 계의 층상 페로브스카이트 구조인 SrBi$_2$Ta$_2$O$_{9}$ (SBT) 박막을 XPS를 이용하여 깊이별 화학 상태 변화를 분석하였다. 아르곤 이온으로 SBT 박막을 식각하면, SBT 박막의 각 구성물들은 가속 Ar$^{+}$ 이온의 에너지에 따라 변화한다. SBT 각 구성물 중 Sr 3d의 화학 상태는 Ar$^{+}$ 이온의 에너지변화에 따라 근소하게 변화한다. 반면에, Ta 4f와 Bi 4f의 화학 상태 변화는 인가되는 Ar$^{+}$ 이온 에너지에 확실하게 의존한다. 특히, Bi 4f는 Sr과 Ta에 비해 낮은 Ar$^{+}$ 이온 에너지에서도 Bi-O의 화학 상태가 금속 Bi 화학 상태로 현저하게 변화한다. 이러한 SBT 박막의 화학 상태 변화는 산호 원자의 선택적인 식각 때문에 발생하며 선택적인 식각은 SBT 박막 내에서 각 구성물과 산소간의 질량 차이와 각 구성물의 열적 안정성에 의존함을 알 수 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.05a
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• pp.189-192
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• 2021

This study applies a deep learning-based long short-term memory(LSTM) model to track tracking technology. In the case of existing track tracking technology, the weight of constant velocity, constant acceleration, stiff turn, and circular(3D) flight is automatically changed when tracking track in real time using LMIPDA based on Kalman filter according to flight characteristics of an aircraft such as constant velocity, constant acceleration, stiff turn, and circular(3D) flight. In this process, it is necessary to improve performance of changing flight characteristic weight, because changing flight characteristics such as stiff turn flight during constant velocity flight could incur the loss of track and decreasing of the tracking performance. This study is for improving track tracking performance by predicting the change of flight characteristics in advance and changing flight characteristic weigh rapidly. To get this result, this study makes deep learning-based Long Short-Term Memory(LSTM) model study the plot and target of simulator applied with radar error model, and compares the flight tracking results of using Kalman filter with those of deep learning-based Long Short-Term memory(LSTM) model.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.