• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.61-72
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• 2002

In this paper, we propose two timing-driven routing algorithms for single-source net and multi-source net as applications of 1-Steiner heuristic algorithm. Using the method of substituting the cost of 1-Steiner heuristic algorithms with interconnection delay, our routing algorithms can route both single-source net and multi-source net which have all critical source-terminal pairs or one critical pair efficiently Our single-source net routing algorithm reduced the average maximum interconnection delay by up to 2.1% as compared with previous single-source routing algorithm, SERT, and 10.6% as compared with SERT-C. and Our multi-source net routing algorithm increased the average maximum interconnection delay by up to 2.7% as compared with MCMD A-tree, but outperforms it by up to average 1.4% when the signal net has only subset of critical node pairs.

• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.40-48
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• 1998

Linear size expanders have been studied in many fields for the practical use, which make it possible to connect large numbers of device chips in both parallel communication systems and parallel computers. One major limitation on the efficiency of parallel computer designs has been the highly cost of parallel communication between processors and memories. Linear order concentrators can be used to construct theoretically optimal interconnection network schemes. Existing explicitly defined constructions are based on expanders, which have large constant factors, thereby rendering them impractical for reasonable sized networks. For these objectives, we use the more detailed matching points in permutation functions, to find out the bigger expansion constant from an equation, $\mid\Gamma_x\mid\geq[1+d(1-\midX\mid/n)]\midX\mid$. This paper presents an improvement of expansion constant on constructing concentrators using expanders, which realizes the reduction of the size in a superconcentrator by a constant factor. As a result, this paper shows an explicit construction of (n, 5, $1-\sqrt{3/2}$) expander. Thus, superconcentrators with 209n edges can be obtained by applying to the expanders of Gabber and Galil's construction.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.131-137
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• 2016

In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

• Communications of the Korean Mathematical Society
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• v.32 no.2
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• pp.435-445
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• 2017

Let D be a directed graph with p vertices and q arcs. A vertex out-magic total labeling is a bijection f from $V(D){\cup}A(D){\rightarrow}\{1,2,{\ldots},p+q\}$ with the property that for every $v{\in}V(D)$, $f(v)+\sum_{u{\in}O(v)}f((v,u))=k$, for some constant k. Such a labeling is called a V-super vertex out-magic total labeling (V-SVOMT labeling) if $f(V(D))=\{1,2,3,{\ldots},p\}$. A digraph D is called a V-super vertex out-magic total digraph (V-SVOMT digraph) if D admits a V-SVOMT labeling. In this paper, we provide a method to find the most vital nodes in a network by introducing the above labeling and we study the basic properties of such labelings for digraphs. In particular, we completely solve the problem of finding V-SVOMT labeling of generalized de Bruijn digraphs which are used in the interconnection network topologies.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.40-51
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• 2009

A paired many-to-many k-disjoint path cover (paired k-DPC) of a graph G is a set of k disjoint paths joining k distinct source-sink pairs in which each vertex of G is covered by a path. In this paper, we investigate disjoint path covers in recursive circulants G($cd^m$,d) with $d{\geq}3$ and tori, and show that provided the number of faulty elements (vertices and/or edges) is f or less, every nonbipartite recursive circulant and torus of degree $\delta$ has a paired k-DPC for any f and $k{\geq}1$ with $f+2k{\leq}{\delta}-1$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.12
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• pp.1229-1235
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• 2015

Scaffold fabrication technology using a 3D printer was developed for damaged bone tissue regeneration. A scaffold for bone tissue regeneration application should be biocompatible, biodegradable, and have an adequate mechanical strength. Moreover, the scaffold should have pores of satisfactory quantity and interconnection. In this study, we used the polymer deposition system (PDS) based on fused deposition modeling (FDM) to fabricate a 3D scaffold. The materials used were polycaprolactone (PCL) and alginic acid sodium salt (sodium alginate, SA). The salt-leaching method was used to fabricate dual pores on the 3D scaffold. The 3D scaffold with dual pores was observed using SEM-EDS (scanning electron microscope-energy dispersive spectroscopy) and evaluated through in-vitro tests using MG63 cells.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.6
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• pp.401-406
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• 2018

In this paper, we present E-band bond-wire modeling and a matching network to compensate for the effect of the bond-wire. The impedance of the bond-wires is extracted using three-dimensional electromagnetic simulation. The matching network was designed using a simple structure. The implemented matching network was verified with a commercial 71~81 GHz LNA IC and an interconnection based on the WR-12 waveguide. The matching network increases the transmission coefficient of the system by up to 4.5 dB, power gain by up to 3.12 dB, $P_{1dB}$ by up to 2.2 dB, and improves the gain flatness by ${\pm}1.07dB$.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.17-26
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• 2017

Electronic packaging technology is a technology that easily connects devices to the outside. The fourth industrial revolution is thought to be possible with the advancement of certain devices. The advancement of these devices must be accompanied by innovations in electronic packaging that connects the devices to the outside world, allowing their performances to be implemented at the system level. In this paper, the development trends of 2.5D/3D technology, heterogeneous integration technology, ultrafine interconnection technology, and heat dissipation technology will be examined, and the development direction of these technologies will be discussed.