• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.16-22
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• 1994

In this paper, transmitter and receiver modules for free space optical interconnection are implemented and characterized. In the transmitter module, bias circuitry which inject current into the direct modulated laser diode is fabricated and in the receiver module, p-i-n diode is integrated with an MMIC amplifying stage. Laser diode has a direct-modulated bandwidth of 2 GHz at 1.4 Ith bias while p-i-n diode and amplifying stage has a bandwidth of 1.3 GHz and 1.5 GHz, repectively. Optical interconnection has a bandwidth of 1.3 GHz and linearly transmit modulated voltage signal up to 1.5 Vp-p. Measured loss of optical interconnection is 5dB which is composed of optoelectronic conversion loss of 15 dB, electrical impedance mismatch loss of 6.7 dB in transmitter module and gain of 18 dB in receiver module. Seperation between transmitter and receiver can be extended up to 50 cm by using a lens.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.111-114
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• 2005

The isolation performance of the S-band single-pole single-throw (SPST) monolithic microwave integrated circuit (MMIC) switch with two different RF-interconnection approaches, microstrip and grounded coplanar waveguide (GCPW) lines, are investigated. On-to-off isolation is improved by 5.8 dB with the GCPW design compared with the microstrip design and additional improvement of 6.9dB is obtained with the coplanar wire-bond interconnection (CWBI) at 3.4 GHz. The measured insertion loss and third-order inter-modulation distortion (IMD3) are less than 2.43 dB over 2.5 CHz $\sim$ 4 GHz and greater than 64 dBc.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.19-26
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• 2014

Through Silicon Via (TSV) technology is the shortest interconnection technology which is compared with conventional wire bonding interconnection technology. Recently, this technology has been also noticed for the miniaturization of electronic devices, multi-functional and high performance. The short interconnection length of TSV achieve can implement a high density and power efficiency. Among the TSV technology, TSV filling process is important technology because the cost of TSV technology is depended on the filling process time and reliability. Various filling methods have been developed like as Cu electroplating method, molten solder insert method and Ti/W deposition method. In this paper, various TSV filling methods were introduced and each filling materials were discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.23-34
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• 2005

Electronic interconnection and packaging is mainly performed in a planar, 2D design style. Further miniaturization and performance enhancement of electronic systems will more and more require the use of 3D interconnection schemes. Key technologies for realizing true 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnect with embedded die. Different applications require different complexities of 3D-interconnectivity. Therefore, different technologies may be used. These can be categorized as a more traditional packaging approach, a wafer-level-packaging, WLP ('above' passivation), approach and a foundry level ('below' passivation) approach. We define these technologies as respectively 3D-SIP, 3D-WLP and 3D-SIC. In this paper, these technologies are discussed in more detail.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• The Journal of Korean Association of Computer Education
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• v.17 no.2
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• pp.115-124
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• 2014

Hypercube and star graph are widely known as interconnection network. The embedding of an interconnection network is a mapping of a network G into other network H. The possibility of embedding interconnection network G into H with a low cost, has an advantage of efficient algorithms usage in network H, which was developed in network G. In this paper, we provide an embedding algorithm between HCN and HON. HCN(n,n) can be embedded into HON($C_{n+1},C_{n+1}$) with dilation 3 and HON($C_d,C_d$) can be embedded into HCN(2d-1,2d-1) with dilation O(d). Also, star graph can be embedded to half pancake's value of dilation 11, expansion 1, and average dilation 8. Thus, the result means that various algorithms designed for HCN and Star graph can be efficiently executed on HON and half pancake, respectively.

• Journal of the Optical Society of Korea
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• v.1 no.1
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• pp.52-59
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• 1997

In this paper, we propose a system design for a parallel3-dimensional optical interconnection network utilizing variable grating mode liquid crystal devices (VGM LCD's) which are optical transducers capable of performing intensity-to-spatial-frequency conversion. The proposed system performs real-time, reconfigurable, but blocking and nonbroadcasting 3-dimensional optical interconnections. The operating principles of the 3-D optical interconnection network are described, and some of the fundamental limitations are addressed. The system presented in this paper can be directly used as a configuration of switching elements for the 2-D optical perfect-shuffle dynamic interconnection network, as well as for a B-ISDN photonic switching system.

• Korean Journal of Optics and Photonics
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• v.13 no.3
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• pp.223-227
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• 2002

Polymeric multi-mode optical waveguides were fabricated for parallel optical interconnection. Waveguide structures were molded by a Ni mold master using a hot embossing technique. The Ni mold master was manufactured by LIGA process. Multimode optical waveguides with a 48$\times$47 ${\mu}{\textrm}{m}$$^2$cross-section were produced by a simple two-step process. The propagation losses of the multimode waveguide measured at 0.85 ${\mu}{\textrm}{m}$ and 1.3 ${\mu}{\textrm}{m}$ wavelengths were 0.38 dB/cm and 0.66 dB/cm, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.134-138
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• 2006

The isolation performance of the S-band single-pole single-throw(SPST) monolithic microwave integrated circuit (MMIC) switch with two different RF-interconnection approaches, microstrip and grounded coplanar waveguide(GCPW) lines, are investigated. On-to-off isolation is improved by 5.8 dB with the GCPW design compared with the microstrip design and additional improvement of 6.9 dB is obtained with the coplanar wire-bond interconnection(CWBI) at a 3.4 GHz. The measured insertion loss and third-order inter-modulation distortion(IMD3) are less than 1.94 dB over $3.2{\sim}3.6\;GHz$ and greater than 64 dBc.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.