• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.132-136
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• 2003

Generally, PM BLDC drive system is necessary that the three Hall-ICs evenly be distributed around the stator circumference and encoder be installed in case of the 3 phase motor. So, the Hall-ICs are set up in this motor to detect the main flux from the rotor, and the output signal from Hall-ICs is used to drive a power transistor to control the winding current. However, instead of using three Hall-ICs and encoder, we used only two Hall-ICs for the permanent magnet rotor position and for the speed feedback signals, and also for a micro controller of 16-bit type (80C196KC) with the 3 phase PM BLDC whose six stator and two rotor designed. Two Hall-IC Hc and $H_B$ are placed on the endplate at 120 degree intervals, and with these elements, we estimated information of the others phase in sequence through a rotating rotor.

• Journal of IKEEE
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• v.16 no.2
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• pp.102-108
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• 2012

3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.6
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• pp.661-668
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• 2012

In this paper, a dual-fed small ICS repeater antenna with high isolation is designed, fabricated, and measured. Bandwidth and gain are optimized by changing the stub lengths near main patch and power divider, and also by changing the size of parasitic patch. To improve the isolation characteristic of the antenna, a dual-feeding method is applied in designing the antenna. The fabricated antenna has a VSWR less than 2, a gain over 7 dBi, and an isolation between the donor and the server antennas less than -65 dB from 1,920~2,170 MHz for 3G mobile communication.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.5
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• pp.549-554
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• 2014

In the paper, we propose a new Signed LMS(Least Mean Square) algorithm for ICS(Interference Cancellation System). The proposed Signed LMS algorithm improved performances by adjusting step size values. At the convergence of 1000 iteration state, the MSE(Mean Square Error) performance of the proposed Signed LMS algorithm with step size of 0.067 is about 3 ~ 18 dB better than the conventional LMS, CMA algorithm. And the proposed Signed LMS algorithm requires 500 ~ 4000 less iterations than the and LMS and CMA algorithms at MSE of -25dB.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.19-25
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• 2009

In this thesis, design effective elimination interference algorithm of ICS repeat system for repeater that improve frequency efficiency. Error convergence speed and accuracy of LMS Algorithm are influenced by reference signal. For improve LMS Algorithm, suggest Adaptive channel estimate algorithm. For using channel characteristic, adaptive channel estimate algorithm make reference signal similar interference signal by convolution operation and complement LMS algorithm demerit. For make channel similar piratical channel, apply Jake's Rayleigh multi-path model that random five path with 130Hz Doppler frequency. LMS algorithm and suggested adaptive channel estimate algorithm that have 16 taps apply to ICS repeat system under Rayleigh multi-path channel, so simulate with MATLAB. According to simulate, ICS repeat system with LMS algorithm show -40dB square error convergent after 150 datas iteration and ICS repeat system with adaptive channel estimate algorithm show -80dB square error convergent after 200 datas iteration. Analyze simulation result, suggested adaptive channel estimate algorithm show more three times iteration performance than LMS algorithm, and 40dB accuracy.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.3
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• pp.52-59
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• 1997

Design and performance of principal four ICs for the 10-Gb/s optical communication system are presented. AlGaAs/GaAs HBTs are basic devices to implement a laser diode driver, apre-amplifier, and a limiting amplifier, and GaInP/GaAs HBTs are used for an AGC amplifier. We fbricated 11.5-GHz LD driver, a pre-amplifier, and a limiting amplifier, an dGaInP/GaAs HBTs are used for an AGC amplifier. We fabricated LD deriver, 10.5 GHz pre amplifier, 7.2 GHz AGC amplifier, and 10.3 GHz limiting amplifier, optimized circuit design and the stabilized MMIC fabrication process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.649-657
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• 2014

In this study, the effects of the frequency-dependent characteristics of through-silicon vias (TSVs) on the performance of 3D ICs are examined by evaluating a typical interconnection structure, which is composed of 32-nm CMOS inverter drivers and receivers connected through TSVs. The frequency-domain model of TSVs is extracted in S-parameter from a 3D electromagnetic (EM) method, where the dimensional variation effect of TSVs can be accurately considered for a comprehensive parameter sweep simulation. A parametric analysis shows that the propagation delay increases with the diameter and height of the TSVs but decreases with the pitch and liner thickness. We also investigate the crosstalk effect between TSVs by testing different signaling conditions. From the simulations, the worst signal integrity is observed when the signal experiences a simultaneously coupled transition in the opposite direction from the aggressor lines. Simulation results for nine-TSV bundles having regular and staggered patterns reveal that the proposed method can characterize TSV-based 3D interconnections of any dimensions and patterns.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.172-179
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• 2015

Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.139-149
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• 2012

A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.