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http://dx.doi.org/10.7471/ikeee.2012.16.2.102

Optimization of Power Bumps and TSVs with Optimized Power Mesh Structure for Power Delivery Network in 3D-ICs  

Ahn, Byung-Gyu (Dept. of Electronics and Computer Engineering, Hanyang University)
Kim, Jae-Hwan (Dept. of Electronics and Computer Engineering, Hanyang University)
Jang, Cheol-Jon (Dept. of Electronics and Computer Engineering, Hanyang University)
Chong, Jong-Wha (Dept. of Electronics and Computer Engineering, Hanyang University)
Publication Information
Journal of IKEEE / v.16, no.2, 2012 , pp. 102-108 More about this Journal
Abstract
3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.
Keywords
3D-IC; power delivery network; bump; TSV;
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