• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.28-30
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• 2009

This paper describes a 3-DTIP(3-D Tour Into Picture) using depth map for a Korean classical painting being composed of persons and landscape. Unlike conventional TIP methods providing 2-D image or video, our proposed TIP can provide users with 3-D stereoscopic contents. Navigating inside a picture provides more realistic and immersive perception. The method firstly makes depth map. Input data consists of foreground object, background image, depth map, foreground mask. Firstly we separate foreground object and background, make each of their depth map. Background is decomposed into polygons and assigned depth value to each vertexes. Then a polygon is decomposed into many triangles. Gouraud shading is used to make a final depth map. Navigating into a picture uses OpenGL library. Our proposed method was tested on "Danopungjun" and "Muyigido" that are famous paintings made in Chosun Dynasty. The stereoscopic video was proved to deliver new 3-D perception better than 2-D video.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.201-204
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• 2006

A system realization for real time DVR system with robust video watermarking algorithm against is attacked various is presented in this paper. The main system is composed of DSP processor and robust video watermarking to be processed at real time on image data and algorithm of the DVR system. The experimental result shows that the processing time takes about 2.5ms on the D1 size image per frame.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1019-1024
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• 2006

A system design and realization for real time DVR system with robust video watermarking algorithm for contents security is presented in this paper. The robust video watermarking is used the intraframe space region and interframe insertion simultaneously, and to be processed at real time on image data and algorithm is used the 64bits special purpose quad DSP processor with assembly and soft pipeline codes. The experimental result shows that the processing time takes about 2.5ms in the D1 image per frame for 60% moving image.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.10
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• pp.1814-1829
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• 2011

In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a given target quality in many video streaming services limited by network bandwidth, such as IPTV services. Each item of video content can be stored on a video streaming server and delivered with the estimated bit rate using the proposed scheme, which consists of the following two steps: 1) In the first step, the complexity of each intra-frame in a given item of video content is computed as a frame feature to extract a group of candidate frames with a lot of bits. 2) In the second step, the bit rate of the video content is determined by applying statistical analysis and hypothesis testing to that group. The experimental results show that our scheme can reduce the bit rate by up to 78% with negligible degradation of subjective quality, especially with the low-complexity videos commonly used in IPTV services.

• The KIPS Transactions:PartB
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• v.18B no.5
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• pp.249-254
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• 2011

FGS (fine granularity scalability) supporting scalability in MPEG-4 Part 2 is a scalable video coding scheme that provides bit-rate adaptation to varying network bandwidth thereby achieving of its optimal video quality. In this paper, we proposed FGS coding scheme which performs one more bit-plane coding for residue signal occured in the enhancement-layer of the basic FGS coding scheme. The experiment evaluated in terms of video quality scalability of the proposed FGS coding scheme by comparing with FGS coding scheme of the MPEG-4 verification model (VM-FGS). The comparison was conducted by analysis of PSNR values of three tested video sequences. The results showed that when using rate control algorithm VM5+, the proposed FGS coding scheme obtained Y, U, V PSNR of 0.4 dB, 9.4 dB, 9 dB averagely higher and when using fixed QP value 17, obtained Y, U, V PSNR of 4.61 dB, 20.21 dB, 16.56 dB averagely higher than the existing VM-FGS. From results, we found that the proposed FGS coding scheme has higher video quality scalability to be able to achieve video quality from minimum to maximum than VM-FGS.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.55-58
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• 2002

This paper describes an RF module for 2.4GHz wireless audio/video transmission. The pre-processed baseband input signals are FM-modulated using a VCO and then transmitted through an antenna after RF filtering. The designed circuits are implemented using a Teflon board of which the size is 52mm${\times}$62mm. The measured maximum output signal levels are around -3dBm and the harmonics are less than -450dBc. The manufactured module consumes 130mA from a 8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.29-36
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• 2003

In this paper, an efficient VLSI architecture for DCTQ module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling 30 frame CIF image for both encoder and decoder simultaneously. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. To reduce the power consumption of DCTQ modu1e, we propose the method not to operate the DCTQ modu1e exploiting the SAE(sum of absolute error) value from motion estimation and cbp(coded block pattern). To reduce the AC/DC prediction memory size, the memory architecture and memory access method for AC/DC prediction block is proposed. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.5
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• pp.513-518
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• 2010

The advancement of information technology along with the proliferation of communication and multimedia has increased the demand of digital contents. Video data of digital contents such as VOD, NOD, Digital Library, IPTV, and UCC are getting more permeated in various application fields. Video data have sequential characteristic besides providing the spatial and temporal information in its 3D format, making searching or browsing ineffective due to long turnaround time. In this paper, we suggest ATVC(Authoring Tool for Video Contents) for solving this issue. ATVC is a video editing tool that detects key frames using visual rhythm and insert metadata such as keywords into key frames via XML tagging. Visual rhythm is applied to map 3D spatial and temporal information to 2D information. Its processing speed is fast because it can get pixel information without IDCT, and it can classify edit-effects such as cut, wipe, and dissolve. Since XML data save key frame information via XML tag and keyword information, it can furnish efficient browsing.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.11 no.4
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• pp.112-120
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• 2012

In this paper, we manufactured the wireless video stream system after we scanned EMI(Electro Magnetic Interference)noise in the system. and then, we analysed the noise frequency in the interface, circuit and PCB(Printed Circuit Board). we suggested EMI noise reduction technique. The applied reduction method is low pass filtering, the internal layer placement for high speed video data line and optimization of the system ground condition. the manufactured system improved about 2 ~ 20[dB] margin for EMI limit 40[dBuV/m] at 30 ~ 230[MHz] and 47[dBuV/m] at 230 ~ 1000[MHz].