• The Bulletin of The Korean Astronomical Society
• /
• v.37 no.2
• /
• pp.188.2-188.2
• /
• 2012

인공위성의 성능을 최대화 하고 긴 운용 수명을 확보하기 위해 부품들의 온도를 특정 범위로 유지 시키는 것은 매우 중요며 이를 위한 온도 모니터링 시스템은 필수적이다. 온도 모니터링 방법은 온도에 따라 저항이 변하는 Thermistor를 이용하는 방법과 출력 전류가 변하는 반도체 센서(AD590)를 이용하는 방법으로 나눌 수 있다. Thermistor의 경우 매우 정밀하게 온도를 모니터링 할 수 있지만 넓은 측정 범위에 대해서는 비선형성 가진다는 단점을 가진다. 이에 반해 반도체 센서의 경우 오차가 크지만 넓은 측정 범위에 대해서도 선형성을 가진다는 장점을 가진다. 본 논문에서는 특정 구간에 대해서 정밀한 온도 모니터링이 필요한 곳에 적용되는 Thermistor를 이용한 온도 모니터링 시스템의 측정 Mechanism에 대해서 고찰한다. 측정 Mechanism의 고찰은 온도에 따른 이산화 된 출력을 내주기 위해 사용되는 Thermistor, Current Source, A/D Converter 등의 하드웨어 적인 부분뿐만 아니라 출력된 값을 이용해 물리적인 온도로 변환시키는데 사용되는 Gain Offset, Calibration Curve 등의 소프트웨어 적인 부분도 포함한다. 또한 하드웨어와 소프트웨어적인 설계 변수를 조절함으로서 온도 모니터링 시스템의 측정범위를 개선하는 방안에 대해 고찰한다. 이렇게 본 논문에서 고찰한 Thermistor를 이용한 저궤도 위성용 온도 모니터링 시스템의 측정범위 개선 방안은 추후 인공위성에 적용되는 온도 모니터링 시스템의 설계에 Design Guide Line을 제시할 것이라고 판단한다.

• Journal of Magnetics
• /
• v.21 no.2
• /
• pp.173-178
• /
• 2016

Six-step commutation control widely used in brushless DC (BLDC) motor can be applied to consequent pole permanent magnet (CPPM) belt starter generator (BSG) with trapezoidal back electromotive force (EMF) in the starter state. However, rotor position detection with three Hall sensors in BLDC motor can hardly be employed in CPPM BSG due to asymmetric flux distribution in each pole side of CPPM BSG. This paper presents a low-cost rotor position detection method for CPPM BSG in which six Hall sensors are proposed to be used based on the analysis of flux distribution by 3D FEA. In the method, the six Hall sensors are divided into three groups and two signals in each group are combined through performing logic operations. In addition, offset angle between back EMF and the related Hall signal can be compensated by moving the Hall sensors. Experiments of a 2 kW CPPM BSG prototype have also been performed to verify the proposed method.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.2
• /
• pp.451-454
• /
• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3181-3183
• /
• 1999

A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.98-107
• /
• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.414-422
• /
• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.189-197
• /
• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.9
• /
• pp.54-61
• /
• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.1 s.343
• /
• pp.49-56
• /
• 2006

This paper describes the design and the verification of IEEE 802.15.4 LR-WPAN 2.4GHz Physical layer for Ubiquitous Sensor Network(USN). We designed the Carrier Frequency Offset(CFO) compensation satisfied the frequency tolerance of IEEE 802.15.4 LR-WPAN and the adaptive matched filter that re-setting of the threshold for the symbol synchronization of the various USN environment. The multiplications is reduced 1/16 by this method each other at i, q phases and has 0.5dB performance improvement in detection probability. Proposed baseband system is designed with verilog HDL and implemented using FPGA prototype board.

• Corrosion Science and Technology
• /
• v.13 no.2
• /
• pp.56-61
• /
• 2014

The purpose of this work is to investigate the effect of dissolved hydrogen concentration on crud deposition onto the fuel cladding surface in the simulated primary environments of a pressurized water reactor. Crud deposition tests were conducted in the dissolved hydrogen concentration range of 5~70 cc/kg at $325^{\circ}C$ for 14 days. Needle-shaped NiO deposits were formed in the hydrogen range of 5~25 cc/kg, while polygonal nickel ferrite deposits were observed at a hydrogen concentration above 35 cc/kg. However, the dissolved hydrogen content seems to have little effect on the amount of crud deposits.