• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.405-413
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• 2013

In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.507-513
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• 2018

Steganography is a technique that uses hidden messages to prevent anyone apart from knowing the existence of a secret message, except the sender and trusted recipients. This paper applies 24 bit color image as cover medium. And a 24-bit color image has three components corresponding to red, green and blue. This paper proposes an image steganography method that uses Triple-A algorithm to hide the secret (Hangul) message by arbitrarily selecting the number of LSB bits and the color channel to be used. This paper divides the secret character into the chosung, jungsung and jongsung, and applies crossover, encryption and arbitrary insertion positions to enhance robustness and confidentiality. Experimental results of the proposed method show that insertion capacity and correlation are excellent and acceptable image quality level. Also, considering the image quality, it was confirmed that the size of LSB should be less than 2.

• ETRI Journal
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• v.34 no.5
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• pp.649-654
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• 2012

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1616-1623
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• 1999

This paper describes error resilient coding scheme is added in WLL system and its application for robust low-bit rate still image transmission over power controlled W-CDA system Rayleigh fading channels. The baseline JPEG compressing methods are uses in image coding over wireless channel. The channel uses Reed-Solomon(RS) outer codes concatenated with convolutional inner codes, and truncated type I hybrid ARQ protocol based on the selective repeat strategy and the RS error detection capability. Simulation results are proved for the statistics of the frame-error bursts of the proposed system in comparison with conventional WLL system. it gains the 2 dB of the Eb/No in same BER.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2415-2423
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• 1999

We propose a new optical method which conceals the data of authorized persons by encryption before they are stored or compared in the pattern recognition system for security systems. This proposed security system is made up of two subsystems : a proposed optical encryption system and a pattern recognition system based on the JTC which has been shown to perform well. In this system, each image of authorized persons as a reference image is stored in memory units through the proposed encryption system. And if a fingerprint image is placed in the input plane of this security system for access to a restricted area, the image is encoded by the encryption system then compared with the encrypted reference image. Therefore because the captured input image and the reference data are encrypted, it is difficult to decrypt the image if one does not know the encryption key bit stream. The basic idea is that the input image is encrypted by performing optical XOR operations with the key bit stream that is generated by digital encryption algorithms. The optical XOR operations between the key bit stream and the input image are performed by the polarization encoding method using the polarization characteristics of LCDs. The results of XOR operations which are detected by a CCD camera should be used as an input to the JTC for comparison with a data base. We have verified the idea proposed here with computer simulations and the simulation results were also shown.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.1
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• pp.24-30
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• 2006

The Controller Area Network (CAN) is being widely used for real-time control application and small-scale distributed computer controller systems. When the stuff bits are generated by bit-stuffing mechanism in the CAN network, it causes jitter including variations in response time and delay In order to eliminate this jitter, stuff bits must be controlled to minimize the response time and to reduce the variation of data transmission time. This paper proposes the method to reduce the stuff bits by restriction of available identifier and bit mask using exclusive OR operation. This da manipulation method are pretty useful to the real-time control strategy with respect to performance. However, the CAN may exhibit unfair behavior under heavy traffic conditions. When there are both high and low priority messages ready for transmission, the proposed precedence priority filtering method allows one low priority message to be exchanged between any two adjacent higher priority messages. In this way, the length of each transmission delays is upper bounded. These procedures are implemented as local controllers for the ISHURO(Inha Semvung Humanoid Robot).

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• Journal of the Korea Society of Computer and Information
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• v.6 no.3
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• pp.56-63
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• 2001

In this paper, The GF(216) multiplier using its subfields GF(24) is designed. This design can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. A finite field serial multiplier using parallel multiplier of subfield takes a less time than serial multiplier and a smaller complexity than parallel multiplier. It has an advatageous feature. A feature between circuit complexity and delay time is compared and simulated using C language.