• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.363-363
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• 2014

Ruthenium (Ru) has attractive material properties due to its promising characteristics such as a low resistivity ($7.1{\mu}{\Omega}{\cdot}cm$ in the bulk), a high work function of 4.7 eV, and feasibility for the dry etch process. These properties make Ru films appropriate for various applications in the state-of-art semiconductor device technologies. Thus, it has been widely investigated as an electrode for capacitor in the dynamic random access memory (DRAM), a metal gate for metal-oxide semiconductor field effect transistor (MOSFET), and a seed layer for Cu metallization. Due to the continuous shrinkage of microelectronic devices, better deposition processes for Ru thin films are critically required with excellent step coverages in high aspect ratio (AR) structures. In these respects, atomic layer deposition (ALD) is a viable solution for preparing Ru thin films because it enables atomic-scale control of the film thickness with excellent conformality. A recent investigation reported that the nucleation of ALD-Ru film was enhanced considerably by using a zero-valent metallorganic precursor, compared to the utilization of precursors with higher metal valences. In this study, we will present our research results on the synthesis and characterization of novel ruthenium complexes. The ruthenium compounds were easy synthesized by the reaction of ruthenium halide with appropriate organic ligands in protic solvent, and characterized by NMR, elemental analysis and thermogravimetric analysis. The molecular structures of the complexes were studied by single crystal diffraction. ALD of Ru film was demonstrated using the new Ru metallorganic precursor and O2 as the Ru source and reactant, respectively, at the deposition temperatures of $300-350^{\circ}C$. Self-limited reaction behavior was observed as increasing Ru precursor and O2 pulse time, suggesting that newly developed Ru precursor is applicable for ALD process. Detailed discussions on the chemical and structural properties of Ru thin films as well as its growth behavior using new Ru precursor will be also presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.10-10
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• 2008

Silicide is inevitable for CMOSFETs to reduce RC delay by reducing the sheet resistance of gate and source/drain regions. Ni-silicide is a promising material which can be used for the 65nm CMOS technologies. Ni-silicide was proposed in order to make up for the weak points of Co-silicide and Ti-silicide, such as the high consumption of silicon and the line width limitation. Low resistivity NiSi can be formed at low temperature ($\sim500^{\circ}C$) with only one-step heat treat. Ni silicide also has less dependence of sheet resistance on line width and less consumption of silicon because of low resistivity NiSi phase. However, the low thermal stability of the Ni-silicide is a major problem for the post process implementation, such as metalization or ILD(inter layer dielectric) process, that is, it is crucial to prevent both the agglomeration of mono-silicide and its transformation into $NiSi_2$. To solve the thermal immune problem of Ni-silicide, various studies, such as capping layer and inter layer, have been worked. In this paper, the Ni-silicide utilizing Pd stacked layer (Pd/Ni/TiN) was studied for highly thermal immune nano-scale CMOSFETs technology. The proposed structure was compared with NiITiN structure and showed much better thermal stability than Ni/TiN.

• Journal of the Korean Institute of Landscape Architecture
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• v.40 no.6
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• pp.161-172
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• 2012

The purpose of this study is to classify, evaluate and grade the existing highway tunnels to increase landscape and natural statistics keeping the structural safety about tunnel gates area and induce the ones that will be constructed in the future by drawing the improvements and restoring the techniques as an environment-friendly. To examine the types of tunnel gate area, total 54 tunnels were investigated by selecting Gyeongbu Expressway, Yeongdong Expressway, and Jungang Expressway. Tunnel entrances and exit ports were classified as a Wall-closed type and Protruding type, which is based on tunnel gate type. Vegetation Landscape types were classified as Multilayer-Same as the surrounding landscape_(MS), Multilayer-Difference of surrounding landscape_(MD), Single layer-Same as the surrounding landscape_(SS), Single layer-Difference of surrounding landscape_(SD), and a Desolate type which based on vegetation layers and environment-friendly. Potential vegetation recovery was identified based on the structural stability and revegetation potential of the tunnel. The factors include the structural stability of the slope height and slope gradient were selected. Revegetation potential was identified as a growth potential. This factor was used in the step to classify vegetation recovery potential of a tunnel. The result, which investigated the types of tunnel entrances and exit parts has found that the most typical in 33 places was a Wall closed type with 61.1% of the total ones. The case of vegetation landscape types was created but different from the ones surrounding it with 85.2% of the total ones. It is judged that the currently constructed vegetation of tunnel entrance and exit parts had put convenience on the safety and management before landscape consideration. In addition, tunnel entrance and exit parts with excellent potential for vegetation recovery were all Protruding type. In addition, it is judged that slope stability can easily obtain growth. Therefore, entrance and exist of the highway tunnels, which will be constructed in the future, should reflect location and the result of the natural and ecological survey in design by performing it in advance and their types, which minimize the damage area range, should be applied to the local characteristics suitably. In addition, the ecologically healthy tunnel construction should be done by introducing active vegetation recovery techniques based on its safety.

• Journal of Korean Society of societal Security
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• v.3 no.2
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• pp.65-71
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• 2010

This study was conducted to provide a method for fire suppression in a central area inside the roof of a wooden cultural property using a gas extinguishing apparatus, which is used as one of fire suppression methods with view to preventing valuable wooden properties inherited from ancestors from being destructed by fire. For a wooden property, it is very difficult to suppress fire when combustion spreads to a central area inside its roof, so it is impossible to put out a fire without destructing it. Such a fire fighting apparatus as a sprinkler, etc., installed in modern structures, is very effective, but the possibility of damaging a cultural property is highly probable after installment and operation, which leads to its low adaptability to a wooden property. Thus, the necessity of developing a fire suppress ion apparatus was raised to minimize the said problem and to obtain the desired results, and the need of making a plan on the installment was also raised based on the results of a test whose validity was proven. The central area inside a roof is a traditional - architectural style which is found in Korean wooden structures only, so it is impossible to discover similar cases in foreign countries. For this reason, this study was conducted to verify the effectiveness by developing a fixed fire suppression apparatus designed considering the speed and effectiveness in fire suppression. This study was sequentially carried out in the following steps. First, a frame for this study was made and the specific plan on a fire suppression method was established. Then, a fire suppression apparatus was installed. In the first step, the effectiveness for fire suppression was tested by installing valve open - punched - main water pores, and in the second step, the same effectiveness was tested by valve opened - punched - injection ports. For a wooden property similar to "Sungnyemun"(Gate of Exalted Ceremonies), its central area of the roof decides whether the fire suppression is successful or not, so the opinions on how to put out a fire were presented in this study, and thus the objective data to establish a method on fire suppression in a wooden structure(cultural property) was secured. Lastly, a scientific verification in the effectiveness for fire suppression measures was presented by installing a gas - fixed fire suppression apparatus.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.