• Title/Summary/Keyword: 2-D interpolation

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Design of a 7-bit 2GSPS Folding/Interpolation A/D Converter with a Self-Calibrated Vector Generator (자체보정 벡터 발생기를 이용한 7-bit 2GSPS A/D Converter의 설계)

  • Kim, Seung-Hun;Kim, Dae-Yun;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.4
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    • pp.14-23
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    • 2011
  • In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

Design of a 1.2V 7-bit 800MSPS Folding-Interpolation A/D Converter with Offset Self-Calibration (Offset Self-Calibration 기법을 적용한 1.2V 7-bit 800MSPS Folding-Interpolation A/D 변환기의 설계)

  • Kim, Dae-Yun;Moon, Jun-Ho;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.3
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    • pp.18-27
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    • 2010
  • In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage,due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

Feedback Control for Multidimensional Linear Systems and Interpolation Problems for Multivariable Holomorphic Functions

  • Malakorn, T.
    • 제어로봇시스템학회:학술대회논문집
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    • 2004.08a
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    • pp.1847-1852
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    • 2004
  • This article provides the connection between feedback stabilization and interpolation conditions for n-D linear systems (n > 1). In addition to internal stability, if one demands performance as a design goal, then there results an n-D matrix Nevanlinna-Pick interpolation problem. Application of recent work on Nevanlinna-Pick interpolation on the polydisk yields a solution of the problem for the 2-D case. The same analysis applies in the n-D case (n > 2), but leads to solutions which are contractive in a norm (the "Schur-Agler norm") somewhat stronger than the $H^{\infty}$ norm. This is an analogous version of the connection between the standard $H^{\infty}$ control problem and an interpolation problem of Nevanlinna-Pick type in the classical 1-D linear time-invariant systems.

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Interpolation Technique for 3-D Conformal Array (3차원 콘포멀 어레이에서의 인터폴레이션 기술의 적용)

  • Kang, Kyung-mook;Seol, Kyung-Eun;Jeon, Junghwan;Koh, Jinhwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.12
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    • pp.1748-1751
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    • 2016
  • In this correspondence, we studied 3D uniform rectangular array as an extension of interpolation technique to compensate the beam pattern of 3D conformal array. The simulation result shows outstanding performance comparing to 2D interpolations.

A 3.3V 8-bit 500MSPS Nyquist CMOS A/D Converter Based on an Interpolation Architecture (Interpolation 기법을 이용한 3.3V 8-bit 500MSPS Nyquist CMOS A/D Converter의 설계)

  • 김상규;송민규
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.67-74
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    • 2004
  • In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track & Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.

Interpolation Error Compensation Method for PMSM Torque Control (PMSM 토크제어를 위한 보간오차 보상방법)

  • Lee, Jung-Hyo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.3
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    • pp.391-397
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    • 2018
  • This paper proposes a interpolation error compensation method for PMSM torque control. In PMSM torque control, two dimensions look-up table(2D-LUT) is used for current reference generation due to its stable and robust torque control performance. However, the stored data in 2D-LUT is discreet, it is impossible to store all over the operation range. To reduce the reference generation error in this region, the 2D-Interpolation method is conventionally used, however, this method still remains the error affected by the number of stored data. Besides, in the case stored by fixed unit, this error is increased in field weakening region because of the small number of stored data. In this paper, analyzing the cause of this interpolation error, and compensating the method to reduce this error. Proposed method is verified by the simulation and experiment.

Image Data Interpolation Based on Adaptive Triangulation

  • Xu, Huan-Chun;Lee, Jung-Sik;Hwang, Jae-Jeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.8C
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    • pp.696-702
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    • 2007
  • This paper proposes a regional feature preserving adaptive interpolation algorithm for natural images. The algorithm can be used in resolution enhancement, arbitrary rotation and other applications of still images. The basic idea is to first scan the sample image to initialize a 2D array which records the edge direction of all four-pixel squares, and then use the array to adapt the interpolation at a higher resolution based on the edge structures. A hybrid approach of switching between bilinear and triangulation-based interpolation is proposed to reduce the overall computational complexity. The experiments demonstrate our adaptive interpolation and show higher PSNR results of about max 2 dB than other traditional interpolation algorithms.

2.5D Quick Turnaround Engraving System through Recognition of Boundary Curves in 2D Images (2D 이미지의 윤곽선 인식을 통한 2.5D 급속 정밀부조시스템)

  • Shin, Dong-Soo;Chung, Sung-Chong
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.20 no.4
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    • pp.369-375
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    • 2011
  • Design is important in the IT, digital appliance, and auto industries. Aesthetic and art images are being applied for better quality of the products. Most image patterns are complex and much lead-time is required to implement them to the product design process. A precise reverse engineering method generating 2.5D engraving models from 2D artistic images is proposed through the image processing, NURBS interpolation and 2.5D reconstruction methods. To generate 2.5D TechArt models from the art images, boundary points of the images are extracted by using the adaptive median filter and the novel MBF (modified boundary follower) algorithm. Accurate NURBS interpolation of the points generates TechArt CAD models. Performance of the developed system has been confirmed through the quick turnaround 2.5D engraving simulation linked with the commercial CAD/CAM system.

A Design and Implementation of Volume Rendering Program based on 3D Sampling (3차원 샘플링에 기만을 둔 볼륨랜더링 프로그램의 설계 및 구현)

  • 박재영;이병일;최흥국
    • Journal of Korea Multimedia Society
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    • v.5 no.5
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    • pp.494-504
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    • 2002
  • Volume rendering is a method of displaying volumetric data as a sequence two-dimensional image. Because this algorithm has an advantage of visualizing structures within objects, it has recently been used to analyze medical images i.e, MRI, PET, and SPECT. In this paper. we suggested a method for creating images easily from sampled volumetric data and applied the interpolation method to medical images. Additionally, we implemented and applied two kinds of interpolation methods to improve the image quality, linear interpolation and cubic interpolation at the sampling stage. Subsequently, we compared the results of volume rendered data using a transfer function. We anticipate a significant contribution to diagnosis through image reconstruction using a volumetric data set, because volume rendering techniques of medical images are the result of 3-dimensional data.

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LiDAR Data Interpolation Algorithm for 3D-2D Motion Estimation (3D-2D 모션 추정을 위한 LiDAR 정보 보간 알고리즘)

  • Jeon, Hyun Ho;Ko, Yun Ho
    • Journal of Korea Multimedia Society
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    • v.20 no.12
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    • pp.1865-1873
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    • 2017
  • The feature-based visual SLAM requires 3D positions for the extracted feature points to perform 3D-2D motion estimation. LiDAR can provide reliable and accurate 3D position information with low computational burden, while stereo camera has the problem of the impossibility of stereo matching in simple texture image region, the inaccuracy in depth value due to error contained in intrinsic and extrinsic camera parameter, and the limited number of depth value restricted by permissible stereo disparity. However, the sparsity of LiDAR data may increase the inaccuracy of motion estimation and can even lead to the result of motion estimation failure. Therefore, in this paper, we propose three interpolation methods which can be applied to interpolate sparse LiDAR data. Simulation results obtained by applying these three methods to a visual odometry algorithm demonstrates that the selective bilinear interpolation shows better performance in the view point of computation speed and accuracy.