• Journal of the Korean Society for Railway
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• v.9 no.1 s.32
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• pp.63-68
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• 2006

This paper proposes a fast Fourier transform(FFT)-based spectral analysis method(SAM) for the dynamic responses of the linear discrete dynamic models with non-proportional damping. The SAM was developed by using discrete Fourier transform(DFT)-theory. To verify the proposed SAM, a three-DOF system with non-proportional viscous damping is considered as an illustrative example. The present SAM is evaluated by comparing the dynamic responses obtained by SAM with those obtained by Runge-Kutta method.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.13-14
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• 2006

In this paper, an efficient butterfly structure for Radix-4 FFT algorithm using DA(Distributed Arithmetic) is proposed. It is shown that DA can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed DA butterfly structure show 61.02% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 64-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 46.1% cell area reduction.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.44-50
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• 2007

In this paper generating algorithms of the conventional chaos code sequences and a new chaos code sequence derived from the real and imaginary parts of FFT of one chaos code sequence, and the time-frequency function characteristics of generated code sequences to measure the signal resolution, are considered. And two chaos based QCSK digital communication systems-one with two different chaos code sequences, the other with FFT of one chaos code sequence-are analyzed in AWGN and fading communication channels. After analyzing the correlation functions of such sequences, the delta-like autocorrelation and near zero crosscorrelation functions of them are very suitable for chaos based spread spectrum communication systems, is verified. Through evaluating the performance of two chaos based QCSK systems above using Monte-Carlo simulation, the improvement of performance in the latter QCSK system compare favorably with that of the former system, is shown.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.1-10
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• 2002

This paper presents the new template based human face recognition methods to improve the recognition performance against scale and in-plane rotation variations of face images. To enhance the recognition performance, the templates are generated by linear or nonlinear operation on multiple images including different scales and rotations of faces. As the invariant features to allow for scale and rotation variations of face images, we adopt the affine transformation, the log-polar mapping, and the log-polar image based FFT. The proposed recognition methods are evaluated in terms of the recognition rate and the processing time. Experimental results show that the proposed template based methods lead to higher recognition rate than the single image based one. The affine transformation based face recognition method shows marginally higher recognition rate than those of the log-polar mapping based method and the log-polar image based FFT, while, in the aspect of processing time, the log-polar mapping based method is the fastest one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.177-180
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• 1986

A high performance Butterfly Arithmetic Unit for FFT processor using two adders is proposed in this papers, which is Based on the distributed and merged arithmetic. Due to simple and easy architecture to implement, this proposed processor is well suited to systolic FFT processor. Simulation was performance using YSLOG (Yonsei logic simulator) on IBM AT computer, to verify logic. By using 3um double Metal CMOS technology,Butterfly arithmetic have been achieved in 1.2 usec.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.72-80
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• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.9
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• pp.1090-1097
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• 2007

The multibeam surveillance radar is a state-of art of 3D radar technology. It applies the stacked beam-on-received realized by a digital beamformer. In this paper, a design concept of beamformer and a method of target altitude extraction for multibeam surveillance radar in the normal environmental condition considering no multipath situations are proposed and investigated. The extraction algorithm based on antenna sine space coordinated system in a FFT digital beamformer is described. The proposed algorithm is simulated by 1 look-up table data and confirmed to have consistent results in accordance with a variety of target altitudes and a full radar frequency range.

• Korean Journal of Agricultural Science
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• v.40 no.1
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• pp.53-59
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• 2013

Analysis of load data during field operations is highly important for optimum design of power drive lines for agricultural tractor. Objective of the paper was to analyze field load data using FFT to determine frequency and the energy levels of meaningful cyclic patterns. Rotary tillage, plowing, baling, and wrapping operations were selected as major field operations of agricultural tractor. An agricultural tractor with power measurement system was used. The tractor was equipped with strain-gauge sensors to measure torque of four driving axles and a PTO axle, speed sensors to measure rotational speed of the driving axles and an engine shaft, pressure sensors to measure pressure of hydraulic pumps, an I/O interface to acquire the sensor signals, and an embedded system to calculate power requirement. In rotary tillage, calculated frequency was decreased as travel speed increased. In baler operation, calculated frequency was increased as PTO speed was increased. The calculated peak frequency levels and expected levels were similar. Results of the study would provide information on power utilization patterns and on better design of power drive lines.

• Journal of Power Electronics
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• v.19 no.1
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• pp.307-315
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• 2019

Condition monitoring has been recognized as an effective and low-cost method to enhance the reliability and improve the maintainability of power electronic converters. In power electronic converters, high-frequency oscillation occurs during the switching transients of power transistors, which is known as ringing. The ringing frequency mainly depends on the values of the parasitic capacitance and stray inductance in the oscillation loop. Although circuit stray inductance is an important factor that leads to the ringing, it does not change with transistor aging. A shift in either the inside inductance or junction capacitance is an important failure precursor for power transistors. Therefore, ringing frequency can be used to monitor the health of power transistors. However, the switching actions of power transistors usually result in a dynamic behavior that can generate oscillation signals mixed with background noise, which makes it hard to directly extract the ringing frequency. A frequency extraction method based on empirical mode decomposition (EMD) and Fast Fourier transformation (FFT) is proposed in this paper. The proposed method is simple and has a high precision. Simulation results are given to verify the ringing analysis and experimental results are given to verify the effectiveness of the proposed method.