• Title/Summary/Keyword: 1단 병렬 시스템

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A Parallel Implementation of Purge Process for Lustre File System (Lustre 파일 시스템을 위한 Purge 기능의 병렬화 구현)

  • Kwon, Min-Woo;Yoon, Jun-Weon;Hong, Tae-Young;Park, Chan-Yeol
    • Proceedings of the Korea Information Processing Society Conference
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    • 2016.10a
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    • pp.64-65
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    • 2016
  • 슈퍼컴퓨터는 대용량의 데이터를 효율적으로 관리하기 위해 Lustre 파일 시스템과 같은 고성능의 병렬 파일 시스템을 이용한다. 한국과학기술정보연구원의 슈퍼컴퓨터 4호기 Tachyon 2차 시스템과 같이 다수의 사용자가 접속하는 슈퍼컴퓨터는 사용자의 데이터가 한없이 누적됨으로 Lustre 파일 시스템의 성능이 저하되는 이슈가 있다. 본 논문에서는 사용자의 데이터가 누적되는 것을 방지하기 위해 장기간 사용하지 않는 데이터를 자동 삭제하는 기능인 Purge기능을 구현하였다. 특히, 기하급수적으로 늘어나는 병렬 파일 시스템의 용량에 대처하기 위해 병렬 컴퓨팅 기술을 이용해 고속 Purge 기능을 구현하였다. 단일 컴퓨팅 노드와 병렬 환경에서 구현한 결과를 비교하였을 때, 단일 컴퓨팅 노드에서는 1,517GB 용량을 지우는데 221.2초가 걸렸으며 16개의 컴퓨팅 노드를 이용한 병렬 환경에서는 49.9초가 걸렸다. 이 결과를 비교했을 때 단일 컴퓨팅 노드에서 구현한 결과 대비 병렬 환경에서 구현했을 때 약 4.4배의 성능향상을 얻을 수 있었다.

Multistage Parallel Nulling-Partial PIC Receiver for Downlink MIMO MC-CDMA Systems (하향링크 다중 안테나 MC-CDMA 시스템을 위한 다단계 병렬 널링 및 병렬 부분 간섭 제거 수신기 설계)

  • 구정회;김경연;심세준;이충용
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.11
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    • pp.1-7
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    • 2004
  • We propose multistage parallel nulling (MPN) partial parallel interference cancellation (PPIC) receiver for downlink multiple-input multiple-output (MIMO) multicarrier (MC)-code division multiple access (CDMA) systems. Though the V-BLAST is a popular MIMO receiver, it shows error floor for multiuser downlink MIMO MC-CDMA systems. The proposed MPN-PPIC receiver does not produce error floor for multiuser case, and achieves substantial performance gains with multistage processing. For single user case, the proposed method also surpasses the V-BLAST receiver with multistage processing for MIMO MC-CDMA systems with chip level interleaving. The system performance of the proposed MPN-PPIC receiver is evaluated through computer simulations.

A Design of CMOS Transceiver for noncoherent UWB Communication system (비동기방식 UWB통신용 CMOS 아날로그 송수신단의 설계)

  • Park, Jung-Wan;Moon, Yong;Choi, Sung-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.71-78
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    • 2005
  • In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

Separation Motion Analysis of Staging System (단분리 시스템의 분리 거동 해석)

  • Yun, Yong-Hyeon;Hong, Seung-Gyu
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.4
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    • pp.1-10
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    • 2006
  • Separation motion analysis of staging system is conducted using combined analysis programs, which include unsteady aerodynamic analysis codes and dynamic motion analysis tools. In this study, the analysis is for the long-rang missile staging system. The purpose of this study is to verify the safety and reliance of the proposed staging system, and to find out the influence of angle of attack perturbation on staging. A structured parallel overset mesh called Chimera grid is used for the simulation of unsteady supersonic Euler flow solver. In addition, unsteady dynamic simulations are also performed.

A Numerical Analysis on Performance of Parallel Type Ejector for High Altitude Simulation (고공 환경 모사를 위한 병렬형 이젝터 구성에 따른 특성 연구)

  • Shin, Donghae;Yu, Isang;Shin, Minku;Oh, Jeonghwa;Ko, Youngsung;Kim, Sunjin
    • Journal of the Korean Society of Propulsion Engineers
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    • v.23 no.1
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    • pp.52-60
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    • 2019
  • In this study, the performance and structure of a parallel ejector comprised of multiple single ejectors were confirmed through numerical analysis. The same design variables (mass suction ratio, compression ratio, and expansion ratio) relevant to the performance of a single ejector were considered in the design of the parallel ejector. Analytical results showed that there was no significant difference in the performance of either system related to the operating mass suction ratio; however, the systemsize was significantly reduced. In addition, it was confirmed that when ejectors of the same performance capacity are arranged in parallel, the combined mass suction ratio is lower than that of the single ejector, allowing a lower pressure to be realized. The results of the analysis indicated that the parallel ejector's performance is not significantly different from that of any single ejector, but confirmed that the parallel ejector can offer a configurationdependent advantage in size and operation.

Analysis of Operation Characteristic of Parallel Cascade Buck-Boost Converter (Cascaded Buck-Boost 컨버터 병렬 구성에 따른 동작특성 분석)

  • Kim, Min-Jung;Kim, Dong-Hee;Lee, Byoung-Kuk
    • Proceedings of the KIPE Conference
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    • 2013.11a
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    • pp.149-150
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    • 2013
  • 비반전 승강압형 토폴로지인 Cascaded Buck-Boost는 크게 Buck단과 Boost단으로 나눌 수 있다. 2상 병렬로 연결되는 Cascaded Buck-Boost 컨버터는 병렬로 연결되는 소자에 따라서 총 3가지의 회로 구성이 가능하며, 제어방법에 따라 1개의 스위치로도 Interleaved 회로처럼 동작이 가능하다. 본 논문에서는 각각의 Cascade Buck-Boost 컨버터의 병렬 구성에 따른 입출력 전압비, 전류리플, 시스템 효율 등을 분석한다.

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Design of Modular DC / DC Converter with Phase-Shifting Topology (위상천이 방식의 모듈형 DC/DC 컨버터 설계)

  • Chai, Yong-Yoong
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.1
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    • pp.81-86
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    • 2019
  • This paper is concerned with a system design that enables a the plurality of switching mode power supplies to be supplied with larger power through a parallel connection. For this purpose, a shunt resistor is placed in series at the output of the constant voltage regulator and the output voltage is sensed and controlled using an arduino. In this paper, two constant-voltage regulators were used for the experiment, but it is possible to generalize for more boards. By using the method that controls the system, the sum of the currents delivered by the two systems to the load was found to be 96% of the current drawn from each board. In case of efficiency, 92.4% efficiency is achieved in the unit board and the efficiency in parallel connection is about 90%.

Parallelization scheme of trajectory index using inertia of moving objects (이동체의 관성을 이용한 궤적 색인의 병렬화 기법)

  • Seo, Young-Duk;Hong, Bong-Hee
    • Journal of Korea Spatial Information System Society
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    • v.8 no.1 s.16
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    • pp.59-75
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    • 2006
  • One of the most challenging and encouraging applications of state-of-the-art technology is the field of traffic control systems. It combines techniques from the areas of telecommunications and computer science to establish traffic information and various assistance services. The support of the system requires a moving objects database system (MODB) that stores moving objects efficiently and performs spatial or temporal queries with time conditions. In this paper, we propose schemes to distribute an index nodes of trajectory based on spatio-temporal proximity and the characteristics of moving objects. The scheme predicts the extendible MBB of nodes of index through the prediction of moving object, and creates a parallel trajectory index. The experimental evaluation shows that the proposed schemes give us the performance improvement by 15%. This result makes an improvement of performance by 50% per one disk.

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a Study on the Hybrid Interference Canceller for MAI Cancellation (다중접속간섭 제거를 위한 혼합형 간섭제거기에 관한 연구)

  • Kim, Jae-Hong;Park, Yong-Wan
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.4
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    • pp.9-16
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    • 2000
  • This paper shows the performance of a multiuser detection DS-CDMA receiver based on of the hybrid scheme of parallel interference cancellation (PIC) and successive interference cancellation (SIC). The proposed hybrid interference cancellation is presented and is compared with existing PIC, SIC and Hybrid It of other type schemes. The performance criteria used for comparison are complexity, delay and average bit error rate (BER) performance obtained by simulation in Rayleigh-fading channel (Jake's model) with additive white Gaussian noise (AWGN). In the proposed hybrid IC, the BER performance approximates the one of SIC and the delay is half of the SIC. And the number of cancellation of the hybrid It is reduced about a fourth.

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Parallel Operation of Three 3 level Neutral-Point-Clamped Converter/Inverters (3 레벨 NPC 컨버터/인버터의 3 병렬 운전)

  • Lee, Seung-Yong;Sul, Seung-Ki
    • Proceedings of the KIPE Conference
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    • 2010.07a
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    • pp.434-435
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    • 2010
  • 본 논문에서는 배전급 고전압(1kV~7.2kV) 계통 연계가 가능한 새로운 3 병렬 3 레벨 NPC(Neutral-Point-Clamped) 컨버터/인버터 회로방식을 제안한다. 이 회로방식은 정격 용량의 1/3 크기를 가지는 NPC 컨버터/인버터 모듈을 3 병렬로 구성하면서 직류단 캐패시터를 병렬 연결하여 중성점 전위 변동을 저감할 수 있는 특징을 가진다. 제안된 3 병렬 3 레벨 NPC 컨버터/인버터는 기존의 NPC 컨버터의 장점을 가지면서 동시에 용량 확장이 가능하고, 하나의 모듈이 고장 상태가 되더라도 부분 운전이 가능하여 시스템의 신뢰성을 증대시킬 수 있다. 본 논문에서는 제안된 중성점 전압 제어 전략을 실험을 통하여 검증한다. 정밀한 중성점 전압 제어를 위한 중성점 전류 제어 방법이 3병렬 구조에서 안정적으로 동작함을 컴퓨터 모의 실험을 통해 검증한다.

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