• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.19-23
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• 2013

본 논문에서는 고속 데이터 처리용 TCAM(Ternary Content Addressable Memory) 설계를 위하여 6T SRAM cell의 안정성 분석 방법에 대해 기술하였다. TCAM은 고속 데이터 처리를 목적으로 하기 때문에 동작 주파수가 높아질수록 필요 시 되는 CMOS 공정의 단위가 작아지게 된다. 공급 전압의 감소는 TCAM 동작에 불안정한 영향을 줄 수 있으므로 SRAM cell 안정성 분석을 통한 TCAM 설계가 필수적이다. 우리는 6T SRAM의 정적 노이즈 마진(SNM)을 측정하여 분석하였고, TCAM의 모든 시뮬레이션은 $0.18{\mu}m$ CMOS 공정을 사용하여 확인하였다.

• 한국정보통신학회논문지
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• 제21권2호
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• pp.345-352
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• 2017

본 논문에서는 전원전압 1V에서 동작하는 산소 및 과산화수소 기반의 혈당전류를 측정할 수 있는 통합형 정전압분극장치를 설계하고 제작하였다. 정전압분극장치는 저전압 OTA, 캐스코드 전류거울 그리고 모드 선택회로로 구성되어 있다. 정전압분극장치는 산소 및 과산화수소 기반에서 혈당의 화학반응으로 발생하는 전류를 측정할 수 있다. OTA의 PMOS 차동 입력단의 바디에는 순방향전압을 인가하여 문턱전압을 낮추어 낮은 전원전압이 가능하도록 하였다. 또한 채널길이변조효과로 인한 전류의 오차를 줄이기 위해 캐스코드 전류거울이 사용되었다. 제안한 저전압 정전압분극장치는 Cadence SPECTRE를 이용하여 설계하였으며, 매그나칩 $0.18{\mu}m$ CMOS 공정을 이용하여 제작되었으며 회로의 크기는 $110{\mu}m{\times}60{\mu}m$이다. 전원전압 1.0V에서 소모전류는 최대 $46{\mu}A$이다. 페리시안화칼륨($K_3Fe(CN)_6$)을 사용하여 제작된 정전압분극장치의 성능을 확인하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.415-418
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• 2004

This paper describes a VLSI implementation of BLAST detection for MIMO-OFDM systems. To achieve high speed requirement, we propose the fully pipeline architecture for BLAST structure. This design is implemented using $0.18{\mu}m$ CMOS technology. For a 4-transmit and 4-receive antennas system, it takes $7.5{\mu}s$ to calculate nulling vector and detection order from 48 channel matrixes.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.281-285
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• 2006

In order to widen the tuning range, capacitive degeneration is applied to fully CMOS LC VCOs. Small signal analysis shows that the fixed MOSFET capacitance seen by the LC tank is smaller than that of the traditional LC VCO, resulting in significant extension in the tuning range. This improvement in the tuning range has been verified through measurement of a 10-GHz LC VCO fabricated by $0.18{\mu}m$ CMOS process. The measured tuning range is from 9.8-GHz to 12-GHz, which is better than those of the reported CMOS LC VCOs in 10-GHz band. The measured phase noise is - 103dBc/Hz at 1MHz offset.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1535-1536
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• 2015

CMOS realization of VDTA (Voltage Differencing Transconductance Amplifier) - Gm and its application in the design of multifunctional filter is presented. Small signal analysis is also done to simplify and depict the realization method. Also the parameters and can be tuned by adjusting the circuit components. The performance of VDTA-Gm amplifier and the designed Band Pass filter are simulated using HSPICE with CMOS $0.18{\mu}m$ process parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.302-308
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• 2011

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip-flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep-submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 ${\mu}m$ CMOS process.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.696-697
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• 2016

본 논문은 5.25-GHz BiCMOS 저 잡음 증폭기를 위한 바이어스 회로를 제안한다. 이러한 회로는 1볼트 전원에서 동작하며, 저전압 및 저전력으로 동작하도록 설계되어 있다. 제안한 회로는 $0.18{\mu}m$ SiGe HBT BiCMOS로 설계하였다. 이러한 회로는 밴드 갭 참조회로 (band-gap reference circuit)를 사용하였다.