• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.20-27
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• 2011

A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

• Magazine of the Korean Society of Agricultural Engineers
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• v.42 no.5
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• pp.133-143
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• 2000

A large scale field test of prefabricated vertical drains was performed to anayze the effect of parameters of the very soft clay at a test site. compression index and the coefficient of horizontal consolidation obtained by back-analysis of settlement data were compared with those obtained by means of laboratory tests. Hyperbolic method, Asaoka meoth and curve fitting method were used to compute final settlement of coefficient of consolidation. The relationships of settlement measurement(Sm) versus design settlement(St) and the measurement consolidation ratio(Um) versus design consolidation (Ut) were shown as Sm=(1.0~1.1) St , Um=(1.13~1.17) Ut at 1.0m spacing of drain and Sm=(0.7~0.8)St, Um= (0.92~0.99) Ut at 1.5 m spacing of drain, respectively . The relationships of the field compression index(CcField) and virgin compression index(vcc lab) were shown as Ccfield =(1.0~1.2)vcc lab . But it was nearly within the same range when considering the error factor with the determination method of virgin compression index and the prediction back-analysis of the settlement data was larger than the coefficient of vertical consolidation, and the ratio of consolidation coefficient (Ch/Cv) was Ch =(2.4~2.9) Cv , Ch=(3.4~4.2) Cv at 1.0m and 1.5m spacing of drain, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.64-70
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• 2009

A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

• Journal of IKEEE
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• v.24 no.4
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• pp.1162-1166
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• 2020

In this paper Low Drop-Out (LDO) regulator that improved load regulation characteristics due to the feedback detection structure. The proposed feedback sensing circuit is added between the output of the LDO's internal error amplifier and the input of the pass transistor to improve the regulation of the delta value coming into the output. It has a voltage value with improved load regulation characteristics than existing LDO regulator. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• 한국해양학회지
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• v.25 no.4
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• pp.217-228
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• 1990

In order to study on the relative significance of nanoplankton in Chonsu Bay, nanoplankton samples were collected and analyzed monthly from September, 1985 to August, 1986. A total of 33 taxa representing 6 phyla, 8 classes, 13 orders, 17 families, 25 genera, 33 species have been identified. Micromonas pusilla, Pedinomonas mikron, Pyramimonas grosii, Chroomonas lateralis, Pyrenomonas salina (=Chromonas salina), chroomonas sp., Cyclotella sp., Gonyaulax sp., unidentified sphericl monads (2-5um and 6-8um in size), and unidentified naviculiod form were common species. the distribution of nanoplankton standing crops showed a great temporal and spartial variations. Nanoplankton standing crops was highest in October, 1985 and lowest in September, 1985. The abundance of nanoplankton in Chonsu Bay may be within the range of that of most coastal areas. Unidentified spherical monada (2-5um and 6-8um in size) were most dominant. Chlorophyll-a concentrations of nanoplankton ranged from 0.81 to 4.78ug/l and daily primary productivity by nanoplankton, 16.4 to 767.2 mgC/m$^2$/day. Nanofraction of total phytoplankton cell number accounted for 38% to 93% (average 6%), chlorophyll-a and primary productivity of nanoplankton 25 to 87% (average 64%) and 9 to 87% (average 53%), respectively. The results implied that nanoplankton could be a considerable contribution to phytoplankton biomass and primary productivity in Chonsu Bay phytoplankton community.

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2009.11a
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• pp.311-312
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• 2009

가압 경수로에서 53,000 MWd/tU으로 연소된 사용후 핵연료의 PCI 영역에 대해 방사선 차폐형 성분 분석기기( Shielded EPMA)를 사용하여 반경방향에 대한 성분분포를 분석하였다. PCI 영역에서 산화층의 두께는 13um 이었으며, 핵분열생성물의 침투 두께는 시료에서 약 10 um 이내로 나타났다. 이 두께에 침투된 핵종의 총 농도는 1~2 wt%로 관찰되었다. 주요핵종은 Cs 0.5~0.7 wt%, Mo 0.2~0.3 wt%, Pd, Ru, Nd, Ce등이 0.1~0.2 wt% 로 관찰되었다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.79-84
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• 2007

In this paper, a fully-integrated low phase noise multi-band CMOS VCO using automatic level controller (ALC) and switched LC tank has been presented. The proposed VCO has been fabricated in a 0.13-um CMOS process. The switched LC tank has been designed with a pair of capacitors and two pairs of inductors switched using MOS switch. By using this structure, four band (2.986 ${\sim}$ 3.161, 3.488 ${\sim}$ 3.763, 4.736 ${\sim}$ 5.093, and 5.35 ${\sim}$ 5.887 GHz) operation is achieved in a single VCO. The VCO with 1.2 V power supply has phase noise of -118.105 dBc/Hz @ 1 MHz at 2.986 GHz and -113.777 dBc/Hz @ 1 MHz at 5.887 GHz, respectively. The reduced phase noise has been approximately -1 ${\sim}$ -3 dBc/Hz @ 1 MHz in the broadest tuning range, 2.986 ${\sim}$ 5.887 GHz. The VCO has consumed 4.2 ${\sim}$ 5.4 mW in the entire frequency band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.