• Korean Journal of Optics and Photonics
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• v.14 no.5
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• pp.545-554
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• 2003

Design of the optical modulator composed of a three-waveguide coupler and CPW traveling-wave electrodes was carried out. Switching phenomena of three-waveguide couplers were analyzed by using the coupled mode theory, and the coupling-lengths of the devices were calculated by means of the FDM. CPW traveling-wave electrodes were analysed by the CMM and SOR simulation technique in order to find the conditions of phase-velocity and impedance matching. Traveling-wave modulators were fabricated on z-cut LiNbO$_3$ substrate. Ti was in-diffused in LiNbO$_3$ to make waveguides and Au electrodes were built on the waveguides by the electrolyte technique. The fabricated modulator chip was end-polished, pig-tailed and packaged in a brass mount with K-connector. The insertion loss and the switching voltage of the optical modulator were about 4㏈ and 19V, respectively. Network analyzer was used to obtain the S parameter and the corresponding RF response. From the measurement, parameters of the traveling-wave electrodes were extracted to be Z$_{c}$= 45 Ω, N$_{eff}$=2.20, and $\alpha$$_{0}$=0.055/cm√GHZ. The measured optical response R($\omega$) was compared with the theoretically estimated one, showing both responses agree well. The measurement results revealed that 3㏈ bandwidth turned out to be about 13 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• Applied Microscopy
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• v.34 no.1
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• pp.51-59
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• 2004

The high acceleration voltage system used in scanning electron microscope were designed and manufactured to test its stability. The Cockcroft-Walton circuits are used both in the cathode voltage up to -30 kV and in the Wehnelt cylinder of -2 kV. The operating voltage of 6 V was applied to the heating of the filament. The wave forms which are formed in the second leg of the high voltage transformer were observed in the oscilloscope with 2 V of DC input. When the high voltages were in the range between 5 kV and 12 kV, the highest value of the stabilities of the generated voltages was obtained as 0.002%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• Journal of The Korean Astronomical Society
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• v.52 no.6
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• pp.227-233
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• 2019

We report the performance of the 13.7-meter Taeduk Radio Astronomy Observatory (TRAO) radio telescope. The telescope has been equipped with a new receiver, SEQUOIA-TRAO, a new backend system, FFT2G, and a new VxWorks operating system. The receiver system features a 16-pixel focal plane array using high-performance MMIC preamplifiers; it shows very low system noise levels, with system noise temperatures from 150 K to 450 K at frequencies from 86 to 115 GHz. With the new backend system, we can simultaneously obtain 32 spectra, each with a velocity coverage of 163 km s^-1 and a resolution of 0.04 km s^-1 at 115 GHz. The new operating system, VxWorks, has successfully handled the LMTMC-TRAO observing software. The main observing method is the on-the-fly (OTF) mapping mode; a position-switching mode is available for small-area observations. Remote observing is provided. The antenna surface has been newly adjusted using digital photogrammetry, achieving a rms surface accuracy better than 130 ㎛. The pointing uncertainty is found to be less than 5" over the entire sky. We tested the new receiver system with multi-frequency observations in OTF mode. The aperture efficiencies are 43±1%, 42±1%, 37±1%, and 33±1%, the beam efficiencies are 45±2%, 48±2%, 46±2%, and 41±2% at 86, 98, 110, and 115 GHz, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.91-102
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• 1996

The multicast routing algorithm is necessary to transmit multimedia traffic efficiently in ATM (asynchronous transfer mode) networks. In this paper, we propose the multicast routing algorithm which is based on VP/VC characteristic. The proposed algorithm is based on VP tree concept and using cost function which is based on VP/VC switching. The cost funication is composed of link cost, delay and weighting factor on delay and the weighting factor is calculated by delay sensitivity of the traffic. The proposed algorithm can choose delay bounded path which satisfies delay constraint, moreover it can choose optimal path among VPs which has the same link cost and satisfying delay constraint. With controlling weighting factor, proposed algorithm can set-up efficient path. When the weighting factor sets to be between 0.8 and 1, experimental results show that the perforance of proposed scheme is approximated to that of cost optimal algorithm and strongly delay optimized algorithm.

• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

• Transactions on Electrical and Electronic Materials
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• v.14 no.5
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.