• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.317-318
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• 2015

본 논문에서는 배터리 충 방전을 위한 고 승압이 가능하며 작은 인덕터를 가진 새로운 양방향 DC-DC 컨버터를 제안한다. 제안 회로는 인덕터를 N1:N2 턴비의 Transformer로 사용하고 Transformer 사이에 스위치, 다이오드를 추가 하였다. 이는 방전 모드 동작에서 입력 전류가 두 개의 Transformer로 전류가 나누어 흐르도록 하였다. 기존 DC-DC 컨버터는 입력 전류가 하나의 인덕터로 흐름으로써 고 전력 시스템에서 높은 전류에 의해 인덕터의 크기가 필요 이상으로 커지는 문제점이 있다. 이를 위해 기존 양방향 회로 방식보다 Transformer의 크기가 0.5배 정도 작은 회로를 제안 하였다. 그리고 기존 방전 Boost 회로는 최대 3배 이상의 승압이 안 되지만 제안 회로에서는 3배 이상의 고 승압이 가능하다. 이를 모의실험 및 실험을 통해 타당성을 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.997-1000
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• 2004

Boolean Satisfiability (SAT)는 전산학의 중요한 문제로서 SAT problem을 풀기 위한 많은 알고리즘과 도구들이 제안되어 왔다. 특히, 지난 몇 년 간 많은 발전을 이루어왔고, 하드웨어 검증과 모델 체킹 등의 분야에서 많이 적용되어 왔다. 여러 문제들을 Conjunctive Normal Form (CNF)로 표현하여 CNF의 특성을 이용하여 SAT 알고리즘이 발전되어 왔다. 그런데, 회로를 CNF로 표현할 때 몇 가지 문제점이 발생하는데 특히 CNF는 회로의 structural information 을 잃어버린다는 것이 큰 문제점이다. 이를 보완하기 위하여 회로의 structural information을 이용하기 위한 많은 연구가 진행되어 왔다. 이러한 대부분의 연구는 회로의 정보를 가지고 있다는 경우에 한정된다. 그러나, 하드웨어 검증에서 회로의 정보 없이 검증해야 하는 경우들도 발생한다. 이 논문은 회로의 정보를 가지고 있지 않을 때 CNF 만으로 회로의 structural information을 추론하는 방법을 제시한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.619-621
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• 2022

COVID-19 사태의 지속화로 재택근무 및 화상 수업의 수요가 증가함에 따라, 화상 회의 서비스에 대한 수요 또한 증가하고 있다. 본 논문은 회의 내용의 텍스트화 및 요약 회의록 생성에 관한 연구를 통해 보다 효율적인 화상 회의 서비스를 제공하고자 한다. WebRTC를 기반으로 화상 회의 서비스를 제공하며, WebSpeech API 를 활용하여 회의 내용을 스크립트화 한다. 회의 스크립트는 BART를 통해 요약본으로 재생성되며, 회의 스크립트와 요약본은 언제든지 열람 및 다운로드가 가능하다. 본 논문은 회의 요약 기능을 제공하는 화상 회의 서비스 MAS (Meeting Auto Summarization)를 제안하며, MAS 의 설계 및 구현 방법을 소개한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.7
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• pp.140-145
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• 1989

In this paper, we present an effective circuit placement method called SOAP (self-organization assisted placement) for rectilinear or arbitrarily-shaped region arised form the layout of ASIC (application specific integrated circuit). Self-organization is a learning algorithm for neural networks proposed by [1] which adjusts weights of synapses connected to neurons such that topologically close neurons are sensitive to inputs that are physically similar. In SOAP, we obtain a good circuit placement result in arbitrarily-shaped region by replacing the block of circuit and the position (x, y coordinates) of the block with the neuron and the weight pair of synapses connected to the neuron, respectively. This method can also be extended to the circuit placement over the nonplanar surface.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.28-36
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• 1998

We have proposed a new non-inverting SOI buffer circuit for the high speed operation at low supply voltage. The body biases of main MOS devices in the proposed circuit are controlled dynamically via subsidiary MOS device connected efficiently to the body terminal. We showed current derivability of the body controlled devices obtained by device simulation and compared with that of conventional SOI devices. Delay time characteristics of the buffer circuit were analyzed by SPICE simulation and compared with those of conventional SOI CMOS buffer circuits. Delay time reduction of the SOI buffer over conventional SOI CMOS buffer with same area is about 36 % at $V_{S}$=1.2 V and $C_{L}$=2 pF. pF.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.16-23
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• 2003

In this paper, we propose an efficient bias circuit of discrete BJT component for hearing aid. The collector feedback bias circuit, widely used for the hearing aid, has a resistor for negative feedback. As the resistor affects AC and DC simultaneously, it is quite difficult to adjust amplifier gain without changing DC bias point. The previous bias circuit also has weak point to be oscillated by the positive feedback of power noise if gain of hearing aid is high. In the proposed circuit, we can reduce the two weak points of the previous circuit by adding a resistor to the collector feedback bias circuit between base and power supply which is $\beta$ times target than the collector resistor. Thus. we can change amplifier gain without changing DC bias point, and reduce power noise gain about 18.5% compare to that of tile previous circuit in the simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.267-273
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• 1998

In this paper, we designed a charge pump with a differential current switching structure and it was made of a MESFET with high speed switching Property compared with CMOSFETs. The charge pump with a differential current switching structure is analyzed about operating property of circuit in high frequency band. Also we propose a method on it's characteristics estimation. The designed circuit is simulated by HSPICE simulator, and in view of the results we think that the charge pump of this study can be used in circuits of 1 GHZ frequency band grade.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• Journal of Practical Engineering Education
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• v.11 no.2
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• pp.143-150
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• 2019

Circuit theory is a systematic study that analyzes and designs the most basic circuits in the field of electrical and electronic engineering. Circuit theory courses are organized as major courses for one or two semesters in the second year of university, so that electrical and electronic engineering students must learn. Experimental courses are being together organized for students to enhance understanding of circuit theory and cultivate the skills and the abilities of circuit design through experiments with actual circuits. This paper is a case study on the teaching method applied in electric circuit design and experiment courses to enhance the learning effect on the experimental education that supports circuit theory. To do this, we propose a 15-week instructional model consisting of theory study, simulation, experiments, and design projects. In the proposed model, the simulation and preliminary experiment preparation process are reinforced to complement the theoretical concept and the design project is introduced to acquire practical circuit design skills as engineers. The results of five-year operation demonstrate the effectiveness of the proposed model.