• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.1-12
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• 2003

In this study, a regime where independent treatment of SETs in transient simulations is valid has been identified quantitatively. It is found that as in the steady-state case, each SET can be treated independently even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance $C_{L}$of the interconnections for the independent treatment of SETs is approximately 10 times larger than that of the steady state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearized equivalent circuit and the solution of master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the time scales down to several tens of pico seconds. The simulation time is also shown to depend on the complexity level of the transient model.l.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.68-77
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• 2003

An improved negative capacitance circuit that cancels out input impedance of a front-end in a bioimpedance measurement and operates stably with a low gain margin has been proposed. Since the proposed circuit comprises wide-band operational amplifiers, selecting operational amplifiers is easy, while an operational amplifier of prefer bandwidth should be chosen to apply conventional circuit. Also, since gain margin can be controlled by a feedback resistor connected serially with a feedback capacitor, gain margin is tuneable with a potentiometer. The input impedance of the proposed circuit is two times larger than that of the conventional circuit and 40-times than that without a negative capacitance circuit. Furthermore, closed-loop phase response of the proposed circuit is better than that of the conventional circuit or without a negative capacitance circuit. Above all, for the proposed circuit, the frequency at which a gain peaking occurs is higher than the frequency at which the loop gain becomes a maximum. Thus, the proposed circuit is not affected by a gain peaking and can be operated with a very low gain margin.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.38 no.8
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• pp.869-874
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• 2014

It is possible to fabricate a three-dimensional (3D) shape using the solid freeform fabrication (SFF) technology. However, there are several problems in applying conventional SFF technologies to the direct manufacturing of a product. Hence, multimaterial SFF is gaining attention. Moreover, a 3D circuit device that is different from a conventional two-dimensional PCB can also be fabricated using multimaterial SFF. In this study, a hybrid system using fused deposition modeling and direct writing was designed for 3D circuit device fabrication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.141-146
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• 2009

In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit haying the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the of ficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum power added efficiency (PAE) of the proposed power amplifier is 82.68% at 1.71GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in $5.08{\sim}9.91%$.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.39-45
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• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.103-107
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• 2019

Recently, many technologies have been developed to realize low power high speed digital data communication and one of them is related to duty cycle correction. In this paper, a low-area duty cycle correction circuit for a voltage-controlled ring generator is proposed. The duty cycle correction circuit is a circuit that corrects the duty cycle using a 180 degree phase difference of a voltage controlled ring oscillator. The proposed low-area duty cycle circuit changes a conventional flip-flop to a true single phase clocking (TSPC) flip-flop And a low-area high-performance circuit is realized. By using TSPC flip-flop instead of general flip-flop, it is possible to realize low-area circuit compared to existing circuit, and it is expected to be used for high-performance circuit for low-power because it is easy to operate at high speed.

• Smart Media Journal
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• v.12 no.1
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• pp.17-23
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• 2023

Design-For-Security (DFS) methodology is to protect integrated circuits from physical attacks, and that can be implemented by adding a security circuit to detect abnormal external access. Among the abnormal accesses called invasive attack, microprobing and FIB circuit editing are classified as the most powerful methods because they have direct access. Microprobing deliberately inject defects into the wire of circuit through probes, or reads and changes data. FIB circuit editing is methods of reconnecting or destroying circuits to neutralize security circuits or to access data. Previous DFS methodology have responded to the attacks by detecting arrival time asymmetry between the two signals or by comparing input/output data based on encrypted communication. This study conducted to reduce hardware overhead, and the proposed circuit detects the reflected signal asymmetry generated through probe or FIB circuit editing and detects the attacks through comparison. Since the proposed security circuit reduces the size and test cycle of the circuit compared to previous studies, the cost used for security can be reduced.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2831-2834
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• 2003

본 논문에서는 PWM 방식을 이용한 THERMO-CON 제어 회로를 제안하였다. 제안한 회로는 정전압을 형성하기 위한 레귤레이터, 신호를 처리하기 위한 op-amp, 삼각파를 만들기 위한 OSC, 그리고 부하의 상태를 감지하기 위한 AMC 와 ISC 로 구성된다. 테스트 결과 서지 전압인가 시 PWM 방식으로 동작하여 회로의 P/sub D/(Power Dissipation)을 줄여 소자의 파괴를 막고 중부하 시(여러 개의 릴레이 구동 시) PWM 동작을 하여 소자의 파괴를 막는다는 것을 확인하였으며, 출력 쇼트 시 쇼트보호회로에 의해 출력 트랜지스터의 파괴를 막는다는 것을 확인하였다.

• Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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• 2002.04a
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• pp.77-80
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• 2002

국내 대부분의 회처리장은 연안에 위치하고 또한 해수를 석탄회 이송수로 사용하고 있다. 따라서 석탄회 -염수의 상호작용에 의하여 석탄회가 풍화가 진행되고 석탄회내의 독성 미량원소 용출특성도 육상처리장과는 다르게 나타날 것으로 예상된다. 그러나, 염수와 석탄회의 반응에 의한 독성미량원소의 용출 및 거동, 그리고 석탄회의 풍화 진행양상에 대한 연구는 국내.외적으로 전무한 실정이다. 따라서, 본 연구에서는 연안 석탄회 매립장에서의 염수-석탄회 반응에 의한 독성미량원소의 용출 및 거동, 그리고 석탄회의 풍화 진행양상에 대한 연구를 수행하였다.