• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.97-102
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• 2001

In computer-aided design, partitioning is task of clustering objects into groups to that a given objection function is optimized It is used at the layout level to fin strongly connected components that can be placed together in order to minimize the layout area and propagation delay. Partitioning can also be used to cluster variables and operation into groups for scheduling and unit selection in high-level synthesis. The most popular algorithms partitioning include the Kernighan-Lin algorithm Fiduccia-Mattheyses heuristic and simulated annealing In this paper we propose a genetic algorithm searching solution space for the circuit partitioning problem. and then compare it with simulated annealing by analyzing the results of implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.721-724
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• 2006

This paper presents a method of the constructing the digital logic switching functions and realizing the circuit design using partition techniques. First of all, we introduce the necessity, background and concepts of the partition design techniques for the digital logic systems. Next, we discuss the definitions that are used in this paper. For the purpose of the circuit design for the digital logic switching functions, we discuss the extraction of the partition functions. Also we describe the construction method of the building block, that is called the building block, based on each partition functions. And we apply the proposed method to the example, and we compare the results with the results of the earlier methods. In result, we describe the control functions, it means that we obtain the effective cost in the digital logic design for any other earlier methods.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.186-193
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• 2003

In recent years the complexity of digital systems has increased dramatically. Although semiconductor manufacturers try to ensure that their products are reliable, it is almost impossible not to have faults somewhere in a system at any given time. As complexity of circuits increases, the necessity of more efficient organized and automated methods for test generation is growing. But, up to now, most of popular and extensive methods for test generation nay be those which sequentially produce an output for an input pattern. They inevitably require a lot of time to search each fault in a system. In this paper, corresponding test patterns are generated through the partitioning method among those based on the exhaustive method. In addition, the method, which can discovers faults faster than other ones that have been proposed ever by inserting a pattern in parallel, is designed and implemented.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.52-57
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• 2001

이 논문에서는 우리는 버스에서의 연속된 데이터 전송 시 발생하는 데이터 값의 천이를 줄이는 새로운 버스-인버트 코딩에 적용 된 것과는 달리, 우리의 기법은 다양한 버스 분할을 시도하여, 각 분할에 독립적으로 버스-인버트 코딩을 적용하여 전체의 데이터 값 천이를 최소화하고자 한다. 실제 회로를 통한 실험에서 기존의 버스-인버트 코딩과 비교하여 우리의 제안한 기법은 데이터 값의 천이를 전체적으로 10%-50% 수준으로 줄일 수 있음을 보여 준다.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.1_2
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• pp.110-123
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• 2001

본 논문에서는 자유 선택 신호 전이 그래프와 비동기 유한 상태기로 기술된 회로 명세로부터 직접 속도 독립 회로를 합성하는 시스템에 대해 기술한다. 기존의 상태 그래프 기반의 합성 시스템은 상태의 수가 지수승으로 증가할 수 있기 때문에 큰 규모의 회로에 대해서는 합성에 실패할 수 있다는 문제점을 가지고 있다. 이를 해결하기 위해 여러 직접 합성 방법들이 제안되었는데, 본 논문의 합성 시스템은 마크드 그래프 분할 방법과 임시 전이의 사용을 허용함으로써 합성할 수 있는 회로의 범위를 넓혔다. 기존의 벤치마크 회로에 대한 실험결과 본 합성 시스템은 기존의 상태 그래프 기반의 합성 시스템에 비하여 현저하게 수행 속도를 단축시킬 수 있었고 기존의 직접 합성 시스템에 비하여 보다 확장된 그리고 보다 실용적인 회로 명세를 처리할 수 있었다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1061-1064
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• 1998

This paper proposes a new topology-based partition method for reconfigurable FPGA systems whose components nd the number of interconnections are predetermined. Here, the partition problem must also consider nets that pass through components such as FPGAs and routing devices to route 100%. We formulate it as a quadratic boolean programming problem suggest a paritition method for it. Experimental results show 100% routing, and up to 15% improvement in the maximum number of I/O pins.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.2
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• pp.31-37
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• 2001

This paper propose ZVS-HB type resonant DC/DC converter have earth different output characteristics using division ratio, not only a source division function but a resonant function and soft switching technique(ZVS, ZCS) instead of conventional source division capacitor. Circuit analysis generally described using normalized parameters most of characteristics with division ratio of source division capacitor. Also, this paper citified a rightfulness of characteristic analysis in comparison with a theoretical values and a experimental values obtain from experiment using Power-MOSFET.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.503-510
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• 1989

This paper represents a method which construct Combinational Mutiple Valued Logic circuits. First, it constructs Combinational Multiple Valued Logic Cell as the input variable, Then, it can be applied to the general case by expanding ti, thus these series of process is simple and regular. The construction theory of Combinational Multiple Valued Logic circuits, representes here has regularity, simplicity and modularity, especially, in case imput variables are incresed this theory also has characteristics of expansion.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.