• Title/Summary/Keyword: 회로구조

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Experimental Study on Temperature-Moisture Combined Measurement System for Slope Failure Monitoring (사면붕괴 모니터링에 사용되는 온도-함수비 복합계측시스템 개발에 관한 실험적 연구)

  • Nam, Jin-Won
    • Journal of the Korea institute for structural maintenance and inspection
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    • v.19 no.2
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    • pp.33-39
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    • 2015
  • Recently, the event of slope failure has been occurring frequently due to rapid climate changes and broad development of infrastructures, and the research for establishment of monitoring and prevention system has been an attentive issue. The major influence factors of slope failure mechanism can be considered moisture and temperature in soil, and the slope failure can be monitored and predicted through the trend of moisture-temperature change. Therefore, the combined sensing technology for the continuous measurement of moisture-temperature with different soil depths is needed for the slope monitoring system. The various independent sensors for each item (i.e. temperature and moisture respectively) have been developed, however, the research for development of combined sensing system has been hardly carried out. In this study, the high-fidelity sensor combing temperature-moisture measurement by using the minimized current consuming temperature circuit and the microwave emission moisture sensor is developed and applied on the slope failure monitoring system. The feasibility of developed monitoring system is verified by various experimental approaches such as standard performance test, mockup test and long-term field test. As a result, the developed temperature-moisture combined measurement system is verified to be measuring and monitoring the temperature and moisture in soil accurately.

Rare Metal Chemistry, Microstructures, and Mineralogy of Coal Ash from Thermal Power Plants of Korea (화력발전소 석탄회의 희유금속화학, 미세구조, 광물학적 특성)

  • Jeong, Gi Young;Kim, Seok-Hwi;Kim, Kangjoo
    • Journal of the Mineralogical Society of Korea
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    • v.28 no.2
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    • pp.147-163
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    • 2015
  • Chemical and mineralogical properties of coal ash samples from the nine thermal power plants of Korea were investigated to acquire basic data for estimating the potential of rare metal recovery. Chemical compositions of coal ash were consistent with those of average shale and foreign coal ashes. However, there were small differences between the metal contents of domestic anthracitic and imported bituminous coal ashes. Unburned coal particles were much abundant in the ash of domestic anthracitic coal. Chalcophile elements were relatively enriched in the fly ash compared to bottom ash. Silicate glass was the major component of coal ash with minor minerals such as quartz, illite (muscovite), mullite, magnetite, lime, and anhydrite. Al and Si were the major components of the glass with varying contents of Ca, Fe, K, and Mg. Glass occurred in a form of porous sphere and irregular pumace-like grain often fused with iron oxide spheres or other glass grains. Iron oxide spheres were fine intergrowth of fast-grown iron oxide crystals in the matrix of silicate glass. Chemical, microstructural, and mineralogical properties would guide successful rare metal recovery from coal ash.

Fabrication of [320×256]-FPA Infrared Thermographic Module Based on [InAs/GaSb] Strained-Layer Superlattice ([InAs/GaSb] 응력 초격자에 기초한 [320×256]-FPA 적외선 열영상 모듈 제작)

  • Lee, S.J.;Noh, S.K.;Bae, S.H.;Jung, H.
    • Journal of the Korean Vacuum Society
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    • v.20 no.1
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    • pp.22-29
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    • 2011
  • An infrared thermographic imaging module of [$320{\times}256$] focal-plane array (FPA) based on [InAs/GaSb] strained-layer superlattice (SLS) was fabricated, and its images were demonstrated. The p-i-n device consisted of an active layer (i) of 300-period [13/7]-ML [InAs/GaSb]-SLS and a pair of p/n-electrodes of (60/115)-period [InAs:(Be/Si)/GaSb]-SLS. FTIR photoresponse spectra taken from a test device revealed that the peak wavelength (${\lambda}_p$) and the cutoff wavelength (${\lambda}_{co}$) were approximately $3.1/2.7{\mu}m$ and $3.8{\mu}m$, respectively, and it was confirmed that the device was operated up to a temperature of 180 K. The $30/24-{\mu}m$ design rule was applied to single pixel pitch/mesa, and a standard photolithography was introduced for [$320{\times}256$]-FPA fabrication. An FPA-ROIC thermographic module was accomplished by using a $18/10-{\mu}m$ In-bump/UBM process and a flip-chip bonding technique, and the thermographic image was demonstrated by utilizing a mid-infrared camera and an image processor.

A Study on the Design of Digital Frequency Discriminator with 3-Channel Delay Lines (3채널 지연선을 가진 디지털주파수판별기의 설계에 관한 연구)

  • Kim, Seung-Woo;Choi, Jae-In;Chin, Hui-cheol
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.6
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    • pp.44-52
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    • 2017
  • In this paper, we propose a DFD (Digital Frequency Discriminator) design that has better frequency discrimination and a smaller size. Electronic warfare equipment can analyze different types of radar signal such as those based on Frequency, Pulse Width, Time Of Arrival, Pulse Amplitude, Angle Of Arrival and Modulation On Pulse. In order for electronic warfare equipment to analyze radar signals with a narrow pulse width (less than 100ns), they need to have a special receiver structure called IFM (Instantaneous Frequency Measurement). The DFD (Digital Frequency Discriminator) is usually used for the IFM. Because the existing DFDs are composed of separate circuit devices, they are bulky, heavy, and expensive. To remedy these shortcomings, we use a three delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$) in the DFD, instead of the four delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$, $64{\lambda}$) generally used in the existing DFDs, and apply the microwave integrated circuit method. To enhance the frequency discrimination, we detect the pulse amplitude and perform temperature correction. The proposed DFD has a frequency discrimination error of less than 1.5MHz, affording it better performance than imported DFDs.

Treatment of Seafood Wastewater using an Improved High-rate Anaerobic Reactor (개선된 고율혐기성 공정을 이용한 수산물 가공폐수처리)

  • Choi, Byeong-Yeong;Choi, Yong-Bum;Han, Dong-Jun;Kwon, Jae-Hyeok
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.12
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    • pp.7443-7450
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    • 2014
  • To resolve shortcomings of high-rate anaerobic processes, such as high upward flow velocity, this study sought to improve the structure of the high-rate anaerobic reactor and evaluate its performance. The improved reactor was manufactured by adjusting the diameter and dividing the reactor into three parts. The evaluation of the structurally improved reactor revealed that the reactor could stabilize a single circuit, and prevent the accumulation of solid matter and leakage of microbes, thereby stabilize the microbes. In the process of anaerobic digestion, an increase in pH and alkalinity within the reactor was presumably attributed to bicarbonate created in the process of organic matter decomposition and due to the re-dissolution of some biogas. To maintain a high rate of organic matter removal, the reactor should be operated with more than 9 hrs of HRT and an organic matter load of under $10.kgTCODcr/m^3{\cdot}d$. The methane gas generated in the anaerobic digestion process showed a high content of 65~83 % at the organic matter load of over $7.7kgTCODcr/m^3{\cdot}d$. per removal of CODcr. The methane quantity was generated at $0.10{\sim}0.23m^3CH_4/kgCOD_{rem}$, showing that it was smaller than the theoretical methane generation amount (0.35) in the STP state. In the latter part of high-rate anaerobic process, an advanced treatment process was required to remove nitrogen.

Low-power FFT/IFFT Processor for Wireless LAN Modem (무선 랜 모뎀용 저전력 FFT/IFFT프로세서 설계)

  • Shin Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.11A
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    • pp.1263-1270
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    • 2004
  • A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz@2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz@2.5-V.

The Effect of Using Analogies in High School Earth Science Classes (고등학교 10학년 과학 '지구의 변동' 단원에서 비유물 활용의 효과)

  • Kim, Sang-Dal;Kim, Jong-Hee;Lee, Ji-Eun
    • Journal of the Korean earth science society
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    • v.24 no.5
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    • pp.393-401
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    • 2003
  • The purpose of this study is to research the effect of using analogies in high school earth science classes. According to the usage of TWA model, three types of teaching strategies were developed: text developer-generated, teacher-generated, and student-generated analogies. The model described in this paper began with a task analysis of highschool science textbooks for grade 10 to identify how the textbook authors used analogies to explain plate tectonics concepts. In this study, 210 students were sampled from first graders of high school. After 7 classes, the consciousness of students was investigated with questionnaires. The results are as follows: 1. Many plate-tectonics analogies are used in high school science textbooks (total 25). Teachers and authors construct effective analogies to help students build on their relevant knowledge by applying it to new knowledge acquired from textbooks. 2. Analysis of the data indicate that instruction using student-generated analogies was more effective than others. But in the class in conveying complicated concepts (ex. transform fault), teacher-generated instruction was effective. Teachers need to be aware of the weakness of using analogies in order to select the most appropriate analogies. 3. Making analogies in general, as well as using analogies have systematic steps. Analogies should be used after considering student's preconception, teacher's consciousness and text author's intention to use analogies as powerful instructional tools.

An Efficient Test Data Compression/Decompression for Low Power Testing (저전력 테스트를 고려한 효율적인 테스트 데이터 압축 방법)

  • Chun Sunghoon;Im Jung-Bin;Kim Gun-Bae;An Jin-Ho;Kang Sungho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.73-82
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    • 2005
  • Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

A 2.5 V 10b 120 MSample/s CMOS Pipelined ADC with High SFDR (높은 SFDR을 갖는 2.5 V 10b 120 MSample/s CMOS 파이프라인 A/D 변환기)

  • Park, Jong-Bum;Yoo, Sang-Min;Yang, Hee-Suk;Jee, Yong;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.39 no.4
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    • pp.16-24
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    • 2002
  • This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(= 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

Small Broadband Phased Array Antenna with Compact Phase-Shift Circuits (간결한 위상 변위 회로를 갖는 소형 광대역 위상 배열 안테나)

  • 한상민;권구형;김영식
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.10
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    • pp.1071-1078
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    • 2003
  • In this paper, the planar, compact, and broadband phased array antenna system for IMT-2000 applications has been investigated. Two methods far designing a low-cost and low-complex beam-farming network are proposed. First, a new compact and broadband phase shifter with continuously controlled phase bits is designed by using parallel coupled lines. Second, its equivalent phase delay line is suggested to be capable of replacing the complex phase shifter with a reference phase bit on a phased array antenna. For the purpose of achieving the broadband system, in addition to the broadband phase shifter, a wide-slot antenna with a ground reflector is utilized as an element antenna. Therefore, the phased array antenna system has achieved compact size, broad bandwidth, and wide steering angle, although it has low complexity and low fabrication cost. The 3${\times}$1 phased array antenna system has a compact size of 1.6 λ${\times}$ l.6 λ, which is the sufficient ground plane of the wide-slot antenna. Experimental results present that the S$\_$11/ has less than 15 dB within the band and its radiation patterns on an E-plane have the capability of steering an antenna beam from -29$^{\circ}$to +30$^{\circ}$.