• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.289-295
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• 2014

In this paper a wideband active balun using advanced phase correction architecture is proposed. The proposed active balun is constructed with each different architecture of active balun combined with the cascode architecture to improve phase correction performance compared with conventional phase correction techniques. Operating over 0.6~2.0 GHz band, the proposed balun shows $10^{\circ}$ of phase error and 2 dB of gain error with 7 mW power consumption from 1.8 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.85-95
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• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• Computational Structural Engineering
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• v.9 no.2
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• pp.93-101
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• 1996

An artificial neural network is a computational model that mimics the biological system of the brain and it consists of a number of interconnected processing units where it can reasonably infer by them. Because the neural network is particularly useful for evaluating systems with a multitude of nonlinear variables, it can be used in experimental results predictions, in structural planning and in optimum design of structures. This paper describes the basic theory related to the neural networks and discusses the applicability of neural networks to predict the ultimate shear capacity of the precast concrete vertical joints by comparing the neural networks with a conventional method such as regression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.987-992
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• 2002

In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.105-114
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• 2000

Delay testing is essential for assurance of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new test method and algorithm are devised which can be used for both stuck-at testing and delay testing. To apply the new test method, a new scan flip-flop is implemented. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased drastically over conventional scan techniques.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1601_1602
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• 2009

본 논문은 SSN(Simultaneous Switching Noise) 이 유전체를 통해 다른 시스템에 유기되는 것을 막기 위한 방법인 EBG(Electromagnetic Band-Gap)에 관한 연구이다. 이에 대한 EBG 구조를 설계하기 위해 PDN(Power Delivery Network)에 주기적인 패턴을 삽입한다. 패키지에 EBG 구조를 적용하기 위해 인쇄 회로기판 범위에서 연구되었던 구조를 변형 및 개조하여 EBG 구조가 내포하고 있는 필터의 차단 주파수의 범위를 넓히며 차단 시작 주파수를 1GHz 아래로 낮추는 소형화 방법을 모색한다. 이 연구에서 실시할 EBG 구조에 대한 간단한 고찰과 인쇄 회로 기판에 적합한 AI-EBG(Alternating impedance Electromagnetic Band-Gap) 구조를 이용한 EBG 의 소형화에 대해 언급하고, 소형화를 위한 3-D EBG 의 설계구조에 대해 설명한다. 그리고 저주파에서 차단특성을 높이기 위한 방법으로 3-D EBG를 사용하고 AI-EBG와 비교하여 차단특성의 변화를 Full-wave 시뮬레이션과 측정으로서 비교한다.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.307-308
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• 2016

본 논문에서는 하나의 감극성 커플드 인덕터 보조 회로를 갖는 발전된 영전압 천이 소프트-스위칭 인버터를 제안한다. 기존에 제안된 소프트-스위칭 인버터의 큰 커패시터나 추가 회로의 필요성과 같은 구조적 단점을 극복하였다. 또한, 하나의 커플드 인덕터 보조 회로를 이용하여 풀-브리지 인버터를 구현하여 보조 회로의 소자 수를 줄여 가격과 부피에서 장점이 있다. 본 논문에서 제안된 회로의 동작 원리와 특성들을 다룰 것이며 시뮬레이션을 통하여 유효성을 검증하였다.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.378-381
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• 2010

본 논문에서는 LDO레귤레이터의 PSRR을 향상 및 전압가변 조정이 가능한 능동 Replica LDO 레귤레이터를 설계하였다. 일반적인 레귤레이터의 PSRR과 회로의 안정성 확보를 위해서 사용된 Replica회로의 경우, 안정된 동작을 유지하기 위해서는 DC 매칭이 이루어져야 한다. 본 논문에서는 능동 Replica LDO회로를 제안하였다. 제안된 회로는 CMFB회로에 의하여 DC 전위의 매칭이 이루어지도록 하였으며, 레귤레이터의 출력전압도 일정한 범위내에서 조정이 가능하다. 또한 HSPCIE시뮬레이션 결과, 제안된 능동 Replica LDO회로의 PSRR특성이 기존 LDO구조에 비하여 좋은 결과을 얻을 수 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.31-38
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• 2003

In this paper, we proposed a new structural AGC(Automatic Gain Control) circuit with extremely short settling time using high speed operation characteristics of a clipper. We investigated its operation characteristics in analysis. We also designed a burst-mode preamplifier for 1.25Gbps EPON systems using commercial foundry and investigated its characteristics by comparing the results of the designed and those of the analyzed. The characteristics of the designed circuit are in good agreement with those of the analyzed. As a result, it is shown that it is possible to realize extremely short settling time of under 1㎱.