• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.668-671
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• 2012

본 논문에서는 차세대 비디오 압축 표준인 HEVC(High Efficiency Video Coding) 복호기의 연산량과 하드웨어 면적을 감소시키기 위하여 화면내 예측 하드웨어 구조를 제안한다. 제안하는 하드웨어 구조는 공통 수식에 대한 연산을 공유하는 공유 연산기를 사용하여 연산량 및 연산기 개수를 감소시키고, $4{\times}4$ PU와 $64{\times}64$ PU의 필터링 수행 여부에 대한 연산을 수행하지 않고 나머지 PU에 대해서는 LUT를 이용하여 연산을 수행하기 때문에 연산량 및 연산 시간을 감소시킨다. 또한 하나의 공통 연산기만을 사용하여 예측 픽셀을 생성하기 때문에 하드웨어 면적이 감소한다. 제안하는 구조를 TSMC 0.18um 공정을 이용하여 합성한 결과 최대 동작 주파수는 100MHz이고, 게이트 수는 140,697이다. $4{\times}4$ PU를 기준으로 제안하는 구조의 처리 사이클 수는 11 사이클로 기존 구조 대비 54% 감소하였고, 16개 참조 픽셀의 필터링 처리를 기준으로 제안하는 구조의 덧셈 연산기 개수는 37개로 표준 draft 6에 비해 22.9% 감소하였다.

• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.49-57
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• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.874-882
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• 2004

MPEG Audio compression algorithm is the international standard for the digital compression of high quality audio using mechanism of the perceptual coding based on psychoacoustic masking. It is necessary to discuss the constraints on designing of common filter banks for MPEG-2 BC and MPEG-2 AAC decoder system, which is not Down yet, mapping audio signals from the time domain into the frequency domain. In this paper, we present an architecture of common synthesis filter whcih can be used for MPEG-2 BC and MPEG-2 AAC decoder using recursive structure. The proposed algorithm is based on recursive architecture that effectively performs common compulsion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.92-97
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• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1387-1394
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• 2011

In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

• Korean Journal of Remote Sensing
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• v.39 no.5_4
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• pp.1145-1153
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• 2023

Urban trees play an important role in absorbing carbon dioxide from the atmosphere, improving air quality, mitigating the urban heat island effect, and providing ecosystem services. To effectively manage and conserve urban trees, accurate spatial information on their location, condition, species, and population is needed. In this study, we propose an algorithm that uses a high-resolution urban tree cover map constructed from deep learning approach to separate trees from the urban land surface and accurately detect tree locations through local maximum filtering. Instead of using a uniform filter size, we improved the tree detection performance by selecting the appropriate filter size according to the tree height in consideration of various urban growth environments. The research output, the location and height of individual trees in human settlement over Suwon, will serve as a basis for sustainable management of urban ecosystems and carbon reduction measures.