Browse > Article
http://dx.doi.org/10.9708/jksci.2010.15.1.001

Processor Design Technique for Low-Temperature Filter Cache  

Choi, Hong-Jun (전남대학교 전자컴퓨터공학부)
Yang, Na-Ra (전남대학교 전자컴퓨터공학부)
Lee, Jeong-A (조선대학교 컴퓨터공학과)
Kim, Jong-Myon (울산대학교 컴퓨터정보통신공학부)
Kim, Cheol-Hong (전남대학교 전자컴퓨터공학부)
Abstract
Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.
Keywords
Embedded Processor; Filter Cache; Modified Filter Cache; Low-power Technique; Low-temperature Technique;
Citations & Related Records
Times Cited By KSCI : 4  (Citation Analysis)
연도 인용수 순위
1 M. Powell, A. Agarwal, T. N. Vijaykumar, B. Falsafi, and K. Roy, "Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping," In Proceedings of International Symposium on Microarchitecture, pp. 54-65, 2001.
2 공준호, 최진항, 이종성, 정성우, "인텔 펜티엄 4와 코어2 듀오의 실행시간과 파워소모량 효율성 비교," 한국컴퓨터정보학회논문지. 제 13권, 제 7호, 165-172쪽, 2008년 12월.   과학기술학회마을
3 SIA, "The International Technology Roadmap for Semiconductors," 2005.
4 D. Brooks andM. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors," In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, 2001.
5 최진항, 공준호, 정의영, 정성우, "온도인지 마이크로프로세서를 위한 듀얼 레지스터파일구조," 정보과학회논문지: 시스템 및 이론 제 35권, 제 11.12호, 510-551쪽, 2008년 12월.
6 Wattch, http://www.eecs.harvard.edu/-dbrooks/
7 Hotspot, http://lava.cs.virginia.edu/HotSpot/
8 SPEC CPU2000 Benchmarks, http://www.specbench.org
9 Origin Pro, http://www.originlab.com/
10 이병석, 김철홍, 이정아, "온도인지 마이크로 프로세서에서 동적 연산 이관을 위한 유닛 선택 기법에 관한 비교분석," 한국컴퓨터종합학술대회 논문집 제36권, 제1호(A), 328-329쪽, 2009년 6월.
11 L. Yeh and R. Chy, "Thermal Management of Microelectronic Equipment," American Society of Mechanical Engineering, 2001.
12 Z. Zhijun, L. R. Hoover, and A. L. Phillips, "Advanced thermal architecture for cooling of high power electronics," Components and Packaging Technologies, IEEE Transactions on, vol. 25, pp. 629-634, 2002.   DOI
13 R. Mahajan, "Thermal Management of CPUs: A Perspective on Trends, Needs, and Opportunities," In Proceedings of the 8th International Workshop on THERMal INvestigations of ICs and Systems, 2002.
14 K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron, "A Case for Thermal-Aware Floorplanning at the Microarchitectural Level," Journal of Instruction-Level Parallelism, Vol. 8, pp. 1-16, 2005.
15 최진항, 이종성, 공준호, 정성우, "실시간 온도 감시를 위한 시뮬레이션 도구의 표현," 한국컴퓨터정보학회 논문지 제 14권. 제 1호, 145-151쪽, 2009년 1월.
16 김종면, 정재욱, 김철홍, "분할 기법을 이용한 저전력 명령어 캐쉬 설계," 정보과학회논문지 : 컴퓨팅의 실제 및 레터 제 13권 제 5호, 241-251쪽, 2007년 10월.   과학기술학회마을
17 J. Kin, M. Gupta, and W. Mangione-Smith, "The Filter Cache: An Energy Efficient Memory Structure," In Proceedings of International Symposiumon Microarchitecture, pp. 184-193, 1997.
18 David H. Albonesi, "Selective Cache Ways: On Demand Cache Resource Allocation," In Proceedings of International Symposium on Microarchitecture, pp. 70-75, 1999.