• Proceedings of the KWS Conference
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• 2001.10a
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• pp.162-164
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• 2001

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.11a
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• pp.81-81
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• 1998

• The Magazine of the IEIE
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• v.22 no.12
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• pp.93-104
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• 1995

디지탈 회로를 구현한 칩 및 보드의 시험 비용을 줄이기 위하여 사용되는 스캔 설계 기술 동향에 대하여 기술하였다. 스캔 설계 기술은 칩 수준에서 먼저 적용되기 시작하였다. 회로의 모든 플립플롭을 스캔할 수 있도록 하는 완전 스캔이 먼저 개발되었고, 최근에는 플립플롭의 일부분만 스캔할 수 있도록 하는 부분 스캔 기술이 활발하게 논의되고 있다. 한편 보드의 시험에 있어서도 보드에 실장되는 칩의 밀도가 증가되고, 표면 실장 기술이 일반화됨에 따라 종래의 시험 기술로는 충분한 시험을 거치는 것이 불가능하게 되었다. 따라서, 칩에 적용되던 기법과 유사한 스캔 설계 기술이 적용되기 시작하였다. 이를 경계 스캔(Boundary Scan)이라고 하는데, 이 기술은 80년대 후반부터 본격적으로 논의되기 시작하였다. 1990년에는 이 기술과 관련된 IEEE의 표준이 제정되어 더욱 많이 적용되는 추세에 있다. 이 논문에서는 이러한 칩 및 보드의 시험을 쉽게하기 위한 스캔 설계 기법의 배경, 발전 과정 및 기술의 내용을 소개한다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.88-93
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• 2003

IC 패키지 기술중 Underfilling 은 칩과 기판사이에 Encapsulant의 표면장력을 이용하여 주입하고 경화시킴으로써 전기적 기계적 보강력을 제공하는 기술로서 시스템 칩의 발전과 함께 차세대 패키징 기술중의 하나이다. 본 연구에서는 기존의 Underfilling 공정을 개선하여 충전시간을 획기적으로 줄일 수 있는 가압식 Underfilling 공정을 이용하여 차세대 반도체 패키징에 적용할 수 있는 가능성을 파악하였다. 이를 위하여 칩과 기판사이에 주입되고 경화되는 Encapsulant의 유동특성을 파악하였다. 가압식 Underfilling기술은 아직까지 상용화되지 않은 미래기술로써 효율적인 몰드 설계를 위하여 Encapsulant 종류에 따라 Gate 위치, Bump Pattern 및 개수, 칩과 기판 사이의 거리, Side Region에 따른 유동특성등의 파악이 중요하다. 본 연구에서는 $DEXTER^{TM}(US)$의 Encapsulant FP4511 을 사용하여 Cavity 내에 Void 를 없앨 수 있는 주입조건을 찾아내고 Underfilling 시간을 감소시킬 수 있는 모사를 진행하였다.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.37-43
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• 2006

Surface roughness and hardness of the electroplated Sn were characterized with variations of electroplating current density and current mode. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the surface roughness of $2.0{\sim}2.4{\mu}m$. The Sn electroplated with pulse current mode exhibited low surface roughness compared one processed with direct current mode. With surface annealing at $300^{\circ}C$ for 3 sec using halogen lamp, surface roughness of the Sn bump was substantially reduced to $1{\mu}m$. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the hardness of 10 Hv. Low contact resistances of $33{\sim}17m{\Omega}$ were obtained for specimens flip-chip bonded with Sn bumps.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.243-251
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• 2005

The distribution of temperature of flip chipped device with peripheral solder bump array was measured with variables, such as the locations and geometries of heater, the size of device, the size of passivation opening. The highest temperature was measured with the larger device, $3.0(mm)\times3.0(mm)$, which has the smallest heater at the center of device and the circular passivation opening. For 2 (watts) power input, the device shows the highest temperature of about $110(^{\circ}C)$. In contrast, the smaller device, $1.5(mm)\times1.8(mm)$, shows that of $90(^{\circ}C)$. In addition to the size effect, the increase of passivation opening size decreased the maximum temperature by about $10(^{\circ}C)$. From the measurement, the temperature of device could be controlled with the size and geometry of heater, the size of device and the size and geometry of passivation opening.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.98-104
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• 2023

The feasibility of an efficient process proposed for Cu-Cu flip-chip bonding was evaluated by forming a porous Cu layer on Cu pillar and conducting thermo-compression sinter-bonding after the infiltration of a reducing agent. The porous Cu layers on Cu pillars were manufactured through a three-step process of Zn plating-heat treatment-Zn selective etching. The average thickness of the formed porous Cu layer was approximately 2.3 ㎛. The flip-chip bonding was accomplished after infiltrating reducing solvent into porous Cu layer and pre-heating, and the layers were finally conducted into sintered joints through thermo-compression. With reduction behavior of Cu oxides and suppression of additional oxidation by the solvent, the porous Cu layer densified to thickness of approximately 1.1 ㎛ during the thermo-compression, and the Cu-Cu flip-chip bonding was eventually completed. As a result, a shear strength of approximately 11.2 MPa could be achieved after the bonding for 5 min under a pressure of 10 MPa at 300 ℃ in air. Because that was a result of partial bonding by only about 50% of the pillars, it was anticipated that a shear strength of 20 MPa or more could easily be obtained if all the pillars were induced to bond through process optimization.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.19-25
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• 2011

The size reduction of the semiconductor chip and the improvement of the electrical performance have been enabled through the introduction of the Cu/Low-K process in modern electronic industries. However, Cu/Low-K has a disadvantage of the physical properties that is weaker than materials used for existing semiconductor manufacture process. It causes many problems in chip manufacturing and package processes. Especially, the delamination between the Cu layer and the low-K dielectric layer is a main defect after the temperature cycles. Since the Cu/Low-K layer is located on the top of the pad of the flip chip, the stress on the flip chip affects the Cu/Low-K layer directly. Therefore, it is needed to improve the underfill process or materials. Especially, it becomes very important to select the underfill to decrease the stress at the flip-chip and to protect the solder bump. We have solved the delamination problem in a 90 nm Cu/Low-K flip-chip package after the temperature cycle by selecting an appropriate underfill.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.37-41
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• 2014

One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.