• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.9-18
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• 2006

In the digital camera system, CMOS image sensor (CIS) is widely used because its size and weight become smaller and power consumption becomes lower. However, there are common problems that colors of the recorded image do not match those of the photographed object and that spectral sensitivity of the CIS used in different cameras varies largely in each case. Therefore, color correction is needed because the spectral sensitivity of the CIS in each color is neither the same color component for most standard colors nor the appropriate color representation for any output devices. In the conventional method, a color correction is empirically obtained by a large number of iterative experiments, but the result is not so satisfied. In this paper, a new method to obtain the efficient color correction matrix for digital camera using CIS is proposed. We obtain camera transfer matrix under the certain white-balance point, and color correction matrix that makes the transfer characteristic of digital camera close to the transfer characteristic of ideal camera is obtained. The experimental results show that the transfer characteristic of digital camera by the proposed method is close to that of the ideal camera. In addition, the image quality of pictures of digital camera using the proposed method is dramatically improved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.91-94
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• 2012

This paper describes an efficient implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit specified in the standard. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 33,218 gates and the estimated throughput is about 640 Mbps at 100 MHz.

• Journal of IKEEE
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• v.20 no.2
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• pp.192-195
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• 2016

In this paper, we present a nanopower CMOS bandgap voltage reference working in sub-threshold region without resisters and bipolar junction transistors (BJT). Complimentary to absolute temperature (CTAT) voltage generator was realized by using two n-MOSFET pair with body bias circuit to make a sufficient amount of CTAT voltage. Proportional to absolute temperature (PTAT) voltage was generated from differential amplifier by using different aspect ratio of input MOSFET pair. The proposed circuits eliminate the use of resisters and BJTs for the operation in a sub-1V low supply voltage and for small die area. The circuits are implemented in 0.18um standard CMOS process. The simulation results show that the proposed sub-BGR generates a reference voltage of 290mV, obtaining temperature coefficient of 92 ppm/$^{\circ}C$ in -20 to $120^{\circ}C$ temperature range. The circuits consume 15.7nW at 0.63V supply.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.54-62
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• 2004

In this paper, we discuss on the design of a current mode CMOS multiplier circuit over $GF(3^m)$. Using the standard basis, we show the variation of vector representation of multiplicand by multiplying primitive element α, which completes the multiplicative process. For the $GF(3^m)$ multiplicative circuit design, we design GF(3) adder and multiplier circuit using current mode CMOS technology and get the simulation results. Using the basic gates - GF(3) adder and multiplier, we build the $GF(3^m)$ multiplier circuit and show the examples for the case m=3. We also propose the assembly of the operation blocks for a complete $GF(3^m)$ multiplier. Therefore, the proposed circuit is easily extensible to other p and m values over $GF(p^m)$ and has advantages for VLSI implementation. We verify the validity of the proposed circuit by functional simulations and the results are provided.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.77-83
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• 2009

In this paper, a selective feedback low-noise amplifier (LNA) has been realized in a $0.18{\mu}m$ CMOS technology to cover a number of wireless multi-standards. By exploiting notch filter, the SF-LNA demonstrates the measured results of the power gain (S21) of 11.5~13dB and the broadband input/output impedance matching of less than -10dB within the frequency bands of 820~960MHz and 1.5~2.5GHz, respectively. The chip dissipates 15mW from a single 1.8V supply, and occupies the area of $1.17\times1.0mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.45-51
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• 2011

This paper presents a wideband low-noise amplifier (LNA) covering 800MHz~5.8GHz for various wireless communication standards by utilizing in a 0.13um CMOS technology. Particularly, the LNA consists of two stages to improve the low-noise characteristics, that is, a cascode input stage and an output buffer with noise cancellation technique. Also, a feedback resistor is exploited to help achieve wideband impedance matching and wide bandwidth. Measure results demonstrate the bandwidth of 811MHz~5.8GHz, the maximum gain of 11.7dB within the bandwidth, the noise figure of 2.58~5.11dB. The chip occupies the area of $0.7{\times}0.9mm^2$, including pads. DC measurements reveal the power consumption of 12mW from a single 1.2V supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.402-403
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• 2011

This paper has proposed a $0.13-{\mu}m$ CMOS RF Front-end transmitter for LTE-Advanced systems. The proposed RF Front-end supports a band 7 (from 2500 MHz to 2570 MHz) in E-UTRA of 3GPP. It can provide a maximum output power level of +10 dBm but it's a normal output power level is +0 dBm considering a low PAPR. The post-layout simulation results show that the quadrature up-conversion mixer and a driver amplifier consumes 14 mA and 28 mA from a 1.2 V supply voltage respectively, while providing a output power level of 0 dBm at the input power level of -13 dBm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.396-397
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• 2011

This paper has proposed a multi-channel low pass filter (LPF) for LTE-Advanced systems. The proposed LPF is an active-RC 5th chebyshev topology with three cut-off frequencies of 5 MHz, 10 MHz, and 40 MHz. A 3-bit tuning circuit has been adopted to prevent variations of each cut-off frequency from process, voltage, and temperature (PVT). To achieve a high cut-off frequency of 40 MHz, an operational amplifier used in the proposed filter has employed a PMOS cross-connection load with a negative impedance. A proposed filter has been implemented in a $0.13-{\mu}m$ CMOS technology and consumes 20.2 mW with a 1.2V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.273-278
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• 2011

This paper has proposed a dual-band transmitter RF Front-end for IMT-Advanced systems which has been implemented in a 0.13-${\mu}m$ CMOS technology. The proposed dual-band transmitter RF Front-End covers 2300~2700 MHz, 3300~3800 MHz frequency ranges which support 802.11, Mobile WiMAX, and IMT-Advanced system. The proposed dual-band transmitter RF Front-End consumes 45 mA from a 1.2 V supply voltage. The performances of the transmitter RF Front-End are verified through post-layout simulations. The simulation results show a +0 dBm output power at 2 GHz band, and +1.3 dBm output power at 3 GHz band.