• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.329-330
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• 2000

기가비트 속도를 지원하는 고속 라우터의 IP 주소 검색은 소프트웨어로 구현할 수 없다는 일부의 믿음과는 달리 소프트웨어만으로도 고속 IP 주소 검색의 구현이 가능하다. 기가비트 라우터의 IP 주소 검색은 최장 프로픽스일치 기법을 사용하여 라우팅 엔트리를 검색하는데, 56Gbps 속도를 지원하기위해서는 평균 513byte의 패킷을 800 nsec 이하의 속도로 처리하여야 한다. 본 논문에서는 범용 펜티엄 프로세서의 캐쉬 크기에 적합한 고속 라우팅을 위한 포워딩 테이블 구조를 제안하였으며, 400 MHz의 페티엄 II 프로세서를 이용한 실험에서 초당 수백만개의 IP 주소 검색을 실현하였다. 제안된 포워딩 테이블은 약 48,000여개의 실제 라우팅 엔트리에 대해 284Kbyte의 매우 작은 크기로 작성되었는데, 이 크기는 펜티엄 프로세서의 L2 케쉬에 저장될 수 있는 작은 크기이다. 제안된 포워딩 테이블을 이용한 평균 검색 시간은 라우팅 테이블 별로 320~530 nsec가 소요되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.11a
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• pp.131-132
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• 2017

CSMA/CA 기반 무선 네트워크에서 장치들은 패킷 충돌을 회피하기 위해 무선 채널을 타 장치가 사용 중인 것을 감지하면 데이터를 전송하지 않고 대기 (Backoff) 한다. 이 Backoff는 Contention Window (CW) 의 크기를 변경하고 Backoff 시간은 이 CW의 크기에 따라 확률적으로 결정된다. 따라서 CW의 크기는 무선 네트워크의 상태를 나타내는 중요한 지표가 될 수 있다. 본 논문에서는 상대적으로 넓은 공간에서 IEEE 802.11a 무선네트워크의 Access Point와 사용자들이 Poisson point process (PPP)를 기반으로 분포되어 Hidden Terminal이 존재할 수 있는 상황에서 CW의 크기 변화를 시뮬레이션을 통해 분석한다.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.74-81
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• 2001

In this paper. the architecture of a high-speed ATM router using ATM switch is studied and the performance of the high-speed ATM router is analyzed through simulation. The high-speed ATM router using ATM switch is able to reduce the load of router and the processing time of a packet in the router. The size of router buffers has been studied through simulation processes for the analysis of performance capacity in due course of making changes in routing time(RT), which is the performance capacity parameters of high-speed ATM routers, flow table size(FS), flow live time(FT) and input circuit efficiencies. The result of this study can be used as the source material for analyzing the suitability of equipment in upgrading networks and applying high-speed ATM routers by using ATM switches.

• Proceedings of the Korea Contents Association Conference
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• 2003.05a
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• pp.223-226
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• 2003

The best way in order to protect the system resource front Distributed Denial of Service(DDoS) attack is cut off the source of DDoS attack with path retracing the packet which transferred by attacker. Packet marking method can not use ICMP cause by using IP identifier field as marking field. And in case of increasing the number of router, retracing method using router ID has the size of marking field's increasing problem. In this paper, we propose that retracing method can be available the ICMP using marking field for option field in IP header and the size of making Held do not change even though the number of router is increased using the mark information which value obtained through XOR operation on IP address.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1353-1358
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• 2014

Tremendous amount of dummy packets are generally generated for faking over a wireless sensor network so as to keep the location privacy of nodes on the communication paths against the global eavesdropping. In this paper, a scoped-flooding protocol is designed for transferring data between each source and mobile sink(aka, basestation) where, the only nodes within the scope are allowed to issue dummy packets at every idle time so that the location privacy of the nodes on the paths is kept and the amount of dummy packets is reduced to the extend of the flooding scope. The size of the flooding diameter can be taken into consideration of the privacy level and the communication cost. We design a detailed specification of the protocol and verify several properties.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.9-16
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• 2004

This paper proposes a performance analysis model of security servers comprising IPSec accelerators. The proposed model is based on a M/M1 queueing system with traffic load of Poisson distribution. The decoding delay has been defined to cover parameters characterizing hardware of security sorrels. Decoding delay values of a commercial IPSec accelerator are extracted yielding less than 15% differences from measured data. The extracted data are used to simulate the server system with the proposed model. The simulated performance of the cryptographic processor BCM5820 is around 75% of the published claimed level. The performance degradation of 3.125% and 14.28% are observed for 64byte packets and 1024byte packets, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.117-124
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• 1998

As window sized increases, the throughput input-buffered packet switch with a window scheme improves on random traffic condition. However, the improvement diminishes quickly under bursty traffic. In this paper, we propose Burst Head Addressable FIFO mechanism and memory structure having search capability in unit of burst header to compensate the sensitiveness of the windowed scheme to bursty traffic. The performance of a input-buffered switch using the proposed Burst Header Addressable FIFO input buffer was analyzed using computer simulations. The maximum throughput of the conventional FIFO scheme approaches an asymptotic value 0.5 as mean burst length increases. The maximum throughput of the proposed scheme is greater than that of the conventional scheme for any mean burst length and window size.

• Journal of the Korea Society for Simulation
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• v.18 no.3
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• pp.91-102
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• 2009

The average window size is most closely related to average throughput. In order to improve fairness, the proposed dropper tries to control the window size of each flow to equal level by intentional packet drop. Intentional packet drop is performed only to the flows that have been occupied bandwidth in a large amount. Because of intentional packet drop, this flow cut down its transmission rate to a half. Accordingly, somewhat capacity of core link comes into existence. And other flow can use this new capacity of this link. Hence other flows have more throughput than before. In this paper, we propose the TRC (Transmission Rate Control) Dropper improving the fairness between individual flows of aggregated sources on DiffServ network. It has the fairness improvement mechanism mentioned above paragraph.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1311-1321
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• 2010

Sensor network is used to obtain sensing data in various area. The interval to sense the events depends on the type of target application and the amounts of data generated by sensor nodes are not constant. Many applications exploit long sensing interval to enhance the life time of network but there are specific applications that requires very short interval to obtain fine-grained, high-precision sensing data. If the number of nodes in the network is increased and the interval to sense data is shortened, the amounts of generated data are greatly increased and this leads to increased amount of packets to transfer to the network. To transfer large amount of packets fast, it is necessary that the delay between successive packet transmissions should be minimized as possible. In this paper, we propose SET(SendDoneEventbasedTransmission Technique)which reduces the delay between successive packet transmissions by using SendDone Event which informs that a packet transmission has been completed. In SET, the delay between successive packet transmissions is shortened very much since the transmission of next packet starts at the time when the transmission of previous packet has completed, irrespective of the transmission time. Therefore SET could provide high packet transmission rate given large amount of packets.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.10
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• pp.95-102
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• 2003

The buffering is a promising solution to resolve the contention problem in optical network. we study the packet loss probability and the dimensioning of optical buffer using a Fiber Delay Line for variable length packet. In this paper, we study the relation between the granularity and the loss of FDL buffer in Single-Stage FDL buffer and propose the Single-Bundle Multi-Stage FDL buffer. The Multi-Stage FDL buffer is too early yet to apply to the current backbone network, considering the current technology in view of costs. but we assume that the above restriction will be resolved in these days. The appropriate number of delay and pass line for a dimensioning is based on a amount of occupied time by packets. Once more another multi-stage FDL buffer is proposed, Split-Bundle multi-stage FDL buffer. The Split-Bundle ms-FDL buffer is more feasible for a FDL buffer structure, considering not only a size of switching matrix but also a bulk of switching element. its feasibility will be demonstrated from a loss probability.